SLVSFC9B October   2020  – March 2022 TPS25947

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
      1.      15
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Reverse Polarity Protection
      2. 8.3.2  Undervoltage Lockout (UVLO and UVP)
      3. 8.3.3  Overvoltage Lockout (OVLO)
      4. 8.3.4  Overvoltage Clamp (OVC)
      5. 8.3.5  Inrush Current, Overcurrent, and Short Circuit Protection
        1. 8.3.5.1 Slew Rate (dVdt) and Inrush Current Control
        2. 8.3.5.2 Circuit-Breaker
        3. 8.3.5.3 Active Current Limiting
        4. 8.3.5.4 Short-Circuit Protection
      6. 8.3.6  Analog Load Current Monitor
      7. 8.3.7  Reverse Current Protection
      8. 8.3.8  Overtemperature Protection (OTP)
      9. 8.3.9  Fault Response and Indication (FLT)
      10. 8.3.10 Auxiliary Channel Control (AUXOFF)
      11. 8.3.11 Power Good Indication (PG)
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Single Device, Self-Controlled
    3. 9.3 Typical Application
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Device Selection
        2. 9.3.2.2 Setting Undervoltage and Overvoltage Thresholds
        3. 9.3.2.3 Setting Output Voltage Rise Time (tR)
        4. 9.3.2.4 Setting Power Good Assertion Threshold
        5. 9.3.2.5 Setting Overcurrent Threshold (ILIM)
        6. 9.3.2.6 Setting Overcurrent Blanking Interval (tITIMER)
      3. 9.3.3 Application Curves
    4. 9.4 Active ORing
    5. 9.5 Priority Power MUXing
    6. 9.6 USB PD Port Protection
    7. 9.7 Parallel Operation
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.7 Parallel Operation

Applications which need higher steady current can use 2 TPS25947xx devices connected in parallel as shown in Figure 9-18 below. In this configuration, the first device turns on initially to provide the inrush current limiting. The second device is held in an OFF state by driving its EN/UVLO pin low using the AUXOFF/PG signal of the first device. After the inrush sequence is complete, the first device asserts its AUXOFF/PG pin high and turns on the second device. The second device asserts its AUXOFF/PG signal to indicate when it has turned on fully, thereby indicating to the system that the parallel combination is ready to deliver the full steady state current.

After in steady state, both devices share current nearly equally. There can be a slight skew in the currents depending on the part-to-part variation in the RON as well as the PCB trace resistance mismatch.

GUID-20200915-CA0I-SCM3-KCTZ-SWCJBKFVNL6N-low.gifFigure 9-18 Two Devices Connected in Parallel for Higher Steady State Current Capability

The waveforms below illustrate the behavior of the parallel configuration during start-up as well as during steady state.

GUID-20210327-CA0I-X4NM-MJGS-V3SVPMF4LBC9-low.gif Figure 9-19 Parallel Devices Sequencing During Start-Up
GUID-20210327-CA0I-90LQ-5BKT-DG1S6XXFQVCP-low.gif Figure 9-20 Parallel Devices Load Current During Steady State