SLVSE57C June   2017  – April 2018 TPS2595

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      TPS25953x Overvoltage Clamp Response Time
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Protection (UVP) and Undervoltage Lockout (UVLO)
      2. 8.3.2 Overvoltage Protection
        1. 8.3.2.1 Overvoltage Lockout (OVLO)
        2. 8.3.2.2 Overvoltage Clamp (OVC)
      3. 8.3.3 Inrush Current, Overcurrent and Short Circuit Protection
        1. 8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 8.3.3.2 Active Current Limiting
        3. 8.3.3.3 Short Circuit Protection
      4. 8.3.4 Overtemperature Protection (OTP)
      5. 8.3.5 Fault Indication (FLT )
      6. 8.3.6 Quick Output Discharge (QOD)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable and Fault Pin Functional Mode 1: Single Device, Self-Controlled
      2. 8.4.2 Enable and Fault Pin Functional Mode 2: Single Device, Host-Controlled
      3. 8.4.3 Enable and Fault Pin Functional Mode 2: Multiple Devices, Self-Controlled
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Programming the Current-Limit Threshold: RILM Selection
        2. 9.2.2.2 Undervoltage Lockout Set Point
        3. 9.2.2.3 Setting Output Voltage Ramp Time (TdVdT)
          1. 9.2.2.3.1 Case 1: Start-Up Without Load. Only Output Capacitance COUT Draws Current
          2. 9.2.2.3.2 Case 2: Start-Up With Load. Output Capacitance COUT and Load Draw Current
      3. 9.2.3 Support Component Selection: CIN
      4. 9.2.4 Application Curves
      5. 9.2.5 Controlled Power Down (Quick Output Discharge) using TPS2595x5
      6. 9.2.6 Overvoltage Lockout using TPS259573
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
      2. 12.1.2 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.3.2 Case 2: Start-Up With Load. Output Capacitance COUT and Load Draw Current

When the load draws current during the turnon sequence, there is additional power dissipated. Considering a resistive load during start-up RL(SU), load current ramps up proportionally with increase in output voltage during TdVdT time. Equation 10 to Equation 13 show the average power dissipation in the internal FET during charging time due to resistive load.

Equation 10. TPS2595 tps2595xx-equation-10.gif

Total power dissipated in the device during start-up is Equation 11.

Equation 11. TPS2595 tps2595xx-equation-11.gif

Total current during start-up is given by Equation 12.

Equation 12. TPS2595 tps2595xx-equation-12.gif

If ISTARTUP> ILIMIT, the device limits the current to ILIMIT and the current-limited charging time is determined by Equation 13.

Equation 13. TPS2595 tps2595xx-equation-13.gif

The power dissipation, with and without load, for selected start-up time must not exceed the shutdown limits as shown in Figure 59.

TPS2595 D001_SLVSE57.gifFigure 59. Thermal Shutdown Limit Plot

For the design example under discussion, select ramp-up capacitor CdVdt = OPEN. The default slew rate for CdVdt = OPEN is 38.2 mV/µs. With slew rate of 38.2 mV/µs, the ramp-up time TdVdt for 12 V input is 248 µs.

The inrush current drawn by the load capacitance COUT during ramp-up using Equation 14.

Equation 14. TPS2595 tps2595xx-equation-14.gif

The inrush power dissipation is calculated using Equation 15.

Equation 15. TPS2595 tps2595xx-equation-15.gif

For 229.2 mW of power loss, the thermal shutdown time of the device must not be less than the ramp-up time TdVdt to avoid the false trip at the maximum operating temperature. Figure 59 shows the thermal shutdown limit at TA = 85°C, for 229.2 mW of power, the shutdown time is infinite. Therefore, it is safe to use 248 µs as the start-up time without any load on the output.

The additional power dissipation when a 4 Ω load is present during start-up is calculated using Equation 10.

Equation 16. TPS2595 eq16_lvscq3.gif

The total device power dissipation during start-up is given in Equation 17.

Equation 17. TPS2595 tps2595xx-equation-17.gif

The Figure 59 shows TA = 85°C and the thermal shutdown time for 6.229 W is more than 10 ms, which is well within the acceptable limits to not use an external capacitor CdVdt with a start-up load of 4 Ω.

When COUT is large, there is a need to decrease the power dissipation during start-up. This can be done by increasing the value of the CdVdt capacitor.