SLVSEI3C October   2018  – May 2020 TPS25982

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematics
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Protection (UVLO and UVP)
      2. 8.3.2 Overvoltage Protection (OVP)
      3. 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 8.3.3.2 Circuit Breaker
        3. 8.3.3.3 Active Current Limiting
        4. 8.3.3.4 Short-Circuit Protection
      4. 8.3.4 Overtemperature Protection (OTP)
      5. 8.3.5 Analog Load Current Monitor (IMON)
      6. 8.3.6 Power Good (PG)
      7. 8.3.7 Load Detect/Handshake (LDSTRT)
    4. 8.4 Fault Response
    5. 8.5 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 9.2.2.3 Setting the Undervoltage Lockout Set Point
        4. 9.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 9.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 9.2.2.6 Setting the Load Handshake (LDSTRT) Delay
        7. 9.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        8. 9.2.2.8 Setting the Auto-Retry Delay and Number of Retries
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Optical Module Power Rail Path Protection
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Device Selection
        3. 9.3.1.3 External Component Settings
        4. 9.3.1.4 Voltage Drop
        5. 9.3.1.5 Application Curves
      2. 9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current

When the load draws current during the turn-on sequence, there is additional power dissipated. Considering a resistive load during start-up RL(SU), load current ramps up proportionally with increase in output voltage during TdVdt time. Equation 18 shows the average power dissipation in the internal FET during charging time due to resistive load.

Equation 18. TPS25982 Pd-load_equation.gif

Equation 19 gives the total power dissipated in the device during start-up

Equation 19. TPS25982 Pd-startup_equation.gif

The power dissipation, with and without load, for selected start-up time must not exceed the start-up thermal shutdown limits as shown in Thermal Shutdown Plot During Start-up

TPS25982 D0028_SLVSEI3.gifFigure 53. Thermal Shutdown Plot During Start-up

For the design example under discussion, the output voltage has to be ramped up in 20 ms, which mandates a slew-rate of 0.6 V/ms for a 12 V rail.

The required CdVdt capacitance on dVdt pin to set 0.6 V/ms slew rate can be calculated using Equation 20

Equation 20. TPS25982 Cdvdt_cal_Apps.gif

The dVdt capacitor is subjected to typically VIN+ 4 V during startup. The high voltage bias leads to a drop in the effective capacitor value. So, it is suggested to choose 20% higher than the calculated value, which gives 9.2 nF. Choose closest 10% standard value: 10 nF

The 10 nF CdVdt capacitance sets a slew-rate of 0.46 V/ms and output ramp time TdVdt of 26 ms.

The inrush current drawn by the load capacitance COUT during ramp-up can be calculated using Equation 21

Equation 21. TPS25982 Iinrush_cal_apps.gif

The inrush power dissipation can be calculated using Equation 22

Equation 22. TPS25982 Pdinrush_cal_apps.gif

For 3.9 W of power loss, the thermal shutdown time of the device must be greater than the ramp-up time TdVdt to ensure a successful start-up. Figure 53 shows the start-up thermal shutdown limit. For 3.9 W of power, the shutdown time is approximately 100 ms. So it is safe to use 26 ms as the start-up time without any load on the output.

The additional power dissipation when a 10-Ω load is present during start-up is calculated using Equation 23

Equation 23. TPS25982 Pd-cal-apps.gif

The total device power dissipation during start-up can be calculated using Equation 24

Equation 24. TPS25982 Pdstartup-cal_Apps.gif

From Thermal Shutdown Plot During Start-up, the thermal shutdown time for 6.3 W is approximately 40 ms. It is safe to have 30% margin to allow for variation of system parameters such as load, component tolerance, and input voltage. So it is well within acceptable limits to use the 10 nF for CdVdt capacitor with start-up load of 10 Ω.

When COUT is large, there is a need to decrease the power dissipation during start-up. This can be done by increasing the value of the CdVdt capacitor. A spreadsheet tool TPS25982xx Design Calculator available on the web can be used for iterative calculations.