SLVSEI3C October   2018  – May 2020 TPS25982

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Simplified Schematics
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Undervoltage Protection (UVLO and UVP)
      2. 8.3.2 Overvoltage Protection (OVP)
      3. 8.3.3 Inrush Current, Overcurrent, and Short-Circuit Protection
        1. 8.3.3.1 Slew Rate and Inrush Current Control (dVdt)
        2. 8.3.3.2 Circuit Breaker
        3. 8.3.3.3 Active Current Limiting
        4. 8.3.3.4 Short-Circuit Protection
      4. 8.3.4 Overtemperature Protection (OTP)
      5. 8.3.5 Analog Load Current Monitor (IMON)
      6. 8.3.6 Power Good (PG)
      7. 8.3.7 Load Detect/Handshake (LDSTRT)
    4. 8.4 Fault Response
    5. 8.5 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Standby Power Rail Protection in Datacenter Servers
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
        2. 9.2.2.2 Setting the Current Limit Threshold: RILIM Selection
        3. 9.2.2.3 Setting the Undervoltage Lockout Set Point
        4. 9.2.2.4 Choosing the Current Monitoring Resistor: RIMON
        5. 9.2.2.5 Setting the Output Voltage Ramp Time (TdVdt)
          1. 9.2.2.5.1 Case 1: Start-Up Without Load: Only Output Capacitance COUT Draws Current
          2. 9.2.2.5.2 Case 2: Start-Up With Load: Output Capacitance COUT and Load Draw Current
        6. 9.2.2.6 Setting the Load Handshake (LDSTRT) Delay
        7. 9.2.2.7 Setting the Transient Overcurrent Blanking Interval (tITIMER)
        8. 9.2.2.8 Setting the Auto-Retry Delay and Number of Retries
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 Optical Module Power Rail Path Protection
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Device Selection
        3. 9.3.1.3 External Component Settings
        4. 9.3.1.4 Voltage Drop
        5. 9.3.1.5 Application Curves
      2. 9.3.2 Input Protection for 12-V Rail Applications: PCIe Cards, Storage Interfaces and DC Fans
  10. 10Power Supply Recommendations
    1. 10.1 Transient Protection
    2. 10.2 Output Short-Circuit Measurements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.1 Undervoltage Protection (UVLO and UVP)

The TPS25982 implements Undervoltage Protection on IN to turn off the output in case the applied voltage becomes too low for the downstream load or the device to operate correctly. The Undervoltage Protection has a default internal threshold of VUVP. If needed, it is also possible to set a user defined Undervoltage Protection threshold higher than VUVP using the UVLO comparator on the EN/UVLO pin. Figure 42 and Equation 1 show how a resistor divider from supply to GND can be used to set the UVLO set point for a given voltage supply level.

TPS25982 Circuit-ENUVLO-connection.gifFigure 42. Adjustable Supply UVLO Threshold
Equation 1. TPS25982 Equation-UVLO.gif

The resistors must be sized large enough to minimize the constant leakage from supply to ground through the resistor divider network. At the same time, keep the current through the resistor network sufficiently larger (20x) than the leakage current on the EN/UVLO pin to minimize the error in the resistor divider ratio.