SLVSFQ6A November   2020  – June 2021 TPS2640

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Undervoltage Lockout (UVLO)
      2. 9.3.2 Overvoltage Protection (OVP)
      3. 9.3.3 Reverse Input Supply Protection
      4. 9.3.4 Hot Plug-In and In-Rush Current Control
      5. 9.3.5 Overload and Short Circuit Protection
        1. 9.3.5.1 Overload Protection
          1. 9.3.5.1.1 Active Current Limiting
          2. 9.3.5.1.2 Electronic Circuit Breaker with Overload Timeout, MODE = OPEN
        2. 9.3.5.2 Short Circuit Protection
          1. 9.3.5.2.1 Start-Up With Short-Circuit On Output
        3. 9.3.5.3 FAULT Response
          1. 9.3.5.3.1 Look Ahead Overload Current Fault Indicator
        4. 9.3.5.4 Current Monitoring
        5. 9.3.5.5 IN, OUT, RTN, and GND Pins
        6. 9.3.5.6 Thermal Shutdown
        7. 9.3.5.7 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Step by Step Design Procedure
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Programming Current Monitoring Resistor—RIMON
        4. 10.2.2.4 Setting Output Voltage Ramp Time—(tdVdT)
          1. 10.2.2.4.1 Case 1: Start-Up Without Load—Only Output Capacitance C(OUT) Draws Current During Start-Up
          2. 10.2.2.4.2 Case 2: Start-Up With Load—Output Capacitance C(OUT) and Load Draws Current During Start-Up
          3. 10.2.2.4.3 Support Component Selections—RFLTb and C(IN)
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Acive ORing Operation
      2. 10.3.2 Field Supply Protection in PLC, DCS I/O Modules
      3. 10.3.3 Simple 24-V Power Supply Path Protection
    4. 10.4 Do's and Dont's
  11. 11Power Supply Recommendations
    1. 11.1 Transient Protection
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, V(IN) = 24 V, V(SHDN) = 2 V, R(ILIM) = 120 kΩ, IMON = FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
MIN NOM MAX UNIT
IN AND UVLO INPUT
UVLO_tON(dly) UVLO turnon delay UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dvdt) = open 250 µs
UVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 250 + 14.5 × C(dvdt) µs
UVLO_toff(dly) UVLO turnoff delay UVLO↓ (100 mV below V(UVLOF)) to FLT↓ 10 µs
SHUTDOWN CONTROL INPUT (SHDN)
tSD(dly) SHUTDOWN exit delay SHDN↑ to V(OUT) = 100 mV, C(dvdt) ≥ 10 nF, [C(dvdt) in nF] 250 + 14.5 × C(dvdt) µs
SHDN↑ to V(OUT) = 100 mV, C(dvdt) = open 250 µs
SHUTDOWN entry delay SHDN↓ (below V(SHUTF)) to FLT↓ 10 µs
OVER VOLTAGE PROTECTION INPUT (OVP)
tOVP(dly) OVP exit delay OVP↓ (20 mV below V(OVPF)) to V(OUT) = 100 mV 200 µs
OVP disable delay OVP↑ (20 mV above V(OVPR)) to FLT↓ 6 µs
CURRENT LIMIT
tFASTTRIP(dly) Fast-trip comparator delay I(OUT) > I(FASTRIP) 250 ns
REVERSE PROTECTION COMPARATOR
tREV(dly) Reverse protection comparator delay (V(IN) – V(OUT))↓ (100-mV overdrive below V(REVTH)) to internal FET turn OFF 1.5 µs
(V(IN) – V(OUT))↓ (10-mV overdrive below V(REVTH)) to FLT↓ 45
tFWD(dly) (V(IN) – V(OUT))↑ (10-mV overdrive above V(FWDTH)) to FLT↑ 70
THERMAL SHUTDOWN
tretry Retry delay in TSD 512 ms
OUTPUT RAMP CONTROL (dVdT)
tdVdT Output ramp time SHDN↑ to V(OUT) = 23.9 V, with C(dVdT) = 47 nF 10 ms
SHDN↑ to V(OUT) = 23.9 V, with C(dVdT) = open 1.6
FAULT FLAG (FLT)
tCB(dly) FLT assertion delay in circuit breaker mode MODE = OPEN, delay from I(OUT) > I(OL) to FLT↓ 4 ms
tCBretry(dly) Retry delay in circuit breaker mode MODE = OPEN 540 ms
tPGOODF PGOOD delay (de- glitch) time Falling edge 875 µs
tPGOODR Rising edge, C(dVdT) = open 1400
Rising egde, C(dVdT) ≥ 10 nF, [C(dvdt) in nF] 875 + 20 × C(dVdT)