SLVS227F August   1999  – December 2020

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Device Comparison
  6. 6Pin Configuration and Functions
  7. 7Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings for TPS3123
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Dissipation Rating Table
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Manual Reset ( MR)
      2. 8.3.2 Active-High or Active-Low Output
      3. 8.3.3 Push-Pull or Open-Drain Output
      4. 8.3.4 Watchdog Timer (WDI)
    4. 8.4 Device Functional Modes
  9. 9Device and Documentation Support

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RMR MR pullup resistor (internal) 27 kΩ
IIH High-level input current WDI WDI = VDD = 3.3 V 1 1 μA
MR MR = 0.7 × VDD, VDD = 3.3 V 20 55
IIL Low-level input current WDI WDI = 0 V, VDD = 3.3 V 1 1 μA
MR MR = 0 V, VDD = 3.3 V 80 170
IOH High-level output current
(leakage into RESET pin)		 TPS3126-xx,
TPS3128-xx		 VDD = VOH = 3.3 V 200 nA
VOH High-level output voltage (TPS3123/4/5 only) RESET VDD = 1.5 V, IOH = –1 mA 0.8×VDD V
VDD = 3.3 V, IOH = –4.5 mA
RESET VDD = 0.75 V, IOH = –8 μA
VDD = 1.5 V, IOH = –1 mA
VOL Low-level output voltage RESET VDD = 0.75 V, IOL = 15 μA 0.2 × VDD V
VDD = 1.5 V, IOL = 1.4 mA
RESET VDD = 1.5 V, IOL = 1.4 mA
VDD = 3.3 V, IOL = 3 mA 0.4
VIT– Negative-going input threshold
voltage (1)		 TPS312xJ12 TA = –40°C to +85°C 1.04 1.08 1.12 V
TPS312xG15 1.35 1.40 1.45
TPS312xJ18 1.56 1.62 1.68
TPS312xL30 2.57 2.64 2.71
TPS312xE12 1.10 1.14 1.18
TPS312xE15 1.38 1.43 1.48
TPS312xE18 1.65 1.71 1.77
VHYS Hysteresis at VDD input 1 V < VIT– < 1.4 V 15 mV
1.4 V < VIT– < 2 V 20
2 V < VIT– < 3 V 30
IDD Supply current TPS3123-xx TPS3124-xx TPS3128-xx WDI = VDD,
MR unconnected		 VDD = 0.75 V 14 μA
VDD = 3.3 V 22 30
TPS3125-xx TPS3126-xx (2) MR unconnected VDD = 0.75 V 14
VDD = 3.3 V 18 25
Ci Input capacitance at MR, WDI VI = 0 V to 3.3 V 5 pF
(1) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 μF) should be placed near the supply terminal.
(2) The supply current during delay time td is typical 5 μA higher.