SLVS227F August   1999  – December 2020

PRODUCTION DATA  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Device Comparison
  6. 6Pin Configuration and Functions
  7. 7Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings for TPS3123
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Dissipation Rating Table
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Timing Diagrams
    9. 7.9 Typical Characteristics
  8. 8Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Manual Reset ( MR)
      2. 8.3.2 Active-High or Active-Low Output
      3. 8.3.3 Push-Pull or Open-Drain Output
      4. 8.3.4 Watchdog Timer (WDI)
    4. 8.4 Device Functional Modes
  9. 9Device and Documentation Support

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Switching Characteristics

at RL = 1 MΩ, CL = 50 pF, TA = +25°C.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ttoutWatchdog time outVDD ≥ VIT– + 0.2 V,
See timing diagram		0.81.42.1s
tdDelay timeVDD > VIT– + 0.2 V,
See timing diagram		100180260ms
tPHLPropagation delay time, high-to-low-level outputMR to RESET delay (TPS3123/5/6/8)VDD ≥ VIT–+ 0.2 V,
VIL = 0.2 × VDD,
VIH = 0.8 × VDD		0.1μs
tPLHPropagation delay time, low-to-high-level outputMR to RESET delay (TPS3125/6)0.1
tPHLPropagation delay time, high-to-low-level outputVDD to RESET delayVIL = VIT– – 0.2 V,
VIH = VIT– + 0.2 V		10μs
tPLHPropagation delay time, low-to-high-level outputVDD to RESET delay (TPS3124/5/6)10