The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer
TPS35-Q1 Precision Voltage Supervisor with Programmable Watchdog Timer
TPS35-Q1
Automotive Nano IQ Precision Voltage Supervisor with Precision Timeout Watchdog Timer
TPS35-Q1 Automotive Nano IQ Precision Voltage Supervisor with Precision Timeout Watchdog Timer
Features
Features
Applications
Applications
Description
Description
Table of Contents
Table of Contents
Revision History
Revision History
Device Comparison
Device Comparison
Pin Configuration and Functions
Pin Configuration and Functions
Specifications
Specifications
Absolute Maximum Ratings
Absolute Maximum Ratings
ESD Ratings
ESD Ratings
Recommended Operating Conditions
Recommended Operating Conditions
Thermal Information
Thermal Information
Electrical Characteristics
Electrical Characteristics
Timing Requirements
Timing Requirements
Switching Characteristics
Switching Characteristics
Timing Diagrams
Timing Diagrams
Typical Characteristics
Typical Characteristics
Detailed Description
Detailed Description
Overview
Overview
Functional Block Diagrams
Functional Block Diagrams
Feature Description
Feature Description
Voltage Supervisor
Voltage Supervisor
Timeout Watchdog Timer
Timeout Watchdog Timer
tWD Timer
tWD Timer
Watchdog Enable Disable Operation
Watchdog Enable Disable Operation
tSD Watchdog Start Up Delay
tSD Watchdog Start Up Delay
SET Pin Behavior
SET Pin Behavior
Manual RESET
Manual RESET
RESET and WDO Output
RESET and WDO Output
Device Functional Modes
Device Functional Modes
Application and Implementation
Application and Implementation
Application Information
Application Information
CRST Delay
CRST Delay
Factory-Programmed watchdog Timing
Factory-Programmed watchdog Timing
Adjustable Capacitor Timing
Adjustable Capacitor Timing
Watchdog Timer Functionality
Watchdog Timer Functionality
Factory-Programmed watchdog Timing
Factory-Programmed watchdog Timing
Adjustable Capacitor Timings
Adjustable Capacitor Timings
Typical Applications
Typical Applications
Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
Design Requirements
Design Requirements
Detailed Design Procedure
Detailed Design Procedure
Setting the Voltage Threshold
Setting the Voltage Threshold
Meeting the Watchdog Timeout Period
Meeting the Watchdog Timeout Period
Setting the Reset Delay
Setting the Reset Delay
Setting the Startup Delay and Output Topology
Setting the Startup Delay and Output Topology
Calculating the RESET Pullup Resistor
Calculating the RESET Pullup Resistor
Power Supply Recommendations
Power Supply Recommendations
Layout
Layout
Layout Guidelines
Layout Guidelines
Layout Example
Layout Example
Device and Documentation Support
Device and Documentation Support
Receiving Notification of Documentation Updates
Receiving Notification of Documentation Updates
Support Resources
Support Resources
Trademarks
Trademarks
Electrostatic Discharge Caution
Electrostatic Discharge Caution
Glossary
Glossary
Mechanical, Packaging, and Orderable Information
Mechanical, Packaging, and Orderable Information
IMPORTANT NOTICE AND DISCLAIMER
IMPORTANT NOTICE AND DISCLAIMER
TPS35-Q1
Automotive Nano IQ Precision Voltage Supervisor with
Precision Timeout Watchdog Timer
TPS35-Q1
Automotive Nano IQ Precision Voltage Supervisor with
Precision Timeout Watchdog TimerTPS35-Q1Automotive Precision Voltage Supervisor with
Timeout
Features
A
20221210
Advance Information to Production
Data release
yes
AEC-Q100 qualified with the following results:
Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Factory programmed or user-programmable watchdog
timeout
±10% Accurate timer (maximum)
Factory programmed: 1 msec to 100 sec
Factory programmed or user-programmable reset
delay
±10% Accurate timer (maximum)
Factory programmed option: 2 msec to 10 sec
Input voltage range: VDD = 1.04 V to
6.0 V
Fixed threshold voltage (VIT-): 1.05 V
to 5.4 V
Threshold voltage available in 50 mV steps
1.2% Voltage threshold accuracy (maximum)
Built-in hysteresis (VHYS): 5%
(typical)
Ultra low supply current: IDD = 250 nA
(typical)
Open-drain, push-pull; active-low outputs
Various programmability options:
Watchdog enable-disable
Watchdog startup delay: no delay to 10 sec
On
the fly timer extension: 1X to 256X
Latched output option
MR functionality
support
Features
A
20221210
Advance Information to Production
Data release
yes
A
20221210
Advance Information to Production
Data release
yes
A
20221210
Advance Information to Production
Data release
yes
A20221210Advance Information to Production
Data releaseyes
AEC-Q100 qualified with the following results:
Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Factory programmed or user-programmable watchdog
timeout
±10% Accurate timer (maximum)
Factory programmed: 1 msec to 100 sec
Factory programmed or user-programmable reset
delay
±10% Accurate timer (maximum)
Factory programmed option: 2 msec to 10 sec
Input voltage range: VDD = 1.04 V to
6.0 V
Fixed threshold voltage (VIT-): 1.05 V
to 5.4 V
Threshold voltage available in 50 mV steps
1.2% Voltage threshold accuracy (maximum)
Built-in hysteresis (VHYS): 5%
(typical)
Ultra low supply current: IDD = 250 nA
(typical)
Open-drain, push-pull; active-low outputs
Various programmability options:
Watchdog enable-disable
Watchdog startup delay: no delay to 10 sec
On
the fly timer extension: 1X to 256X
Latched output option
MR functionality
support
AEC-Q100 qualified with the following results:
Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Factory programmed or user-programmable watchdog
timeout
±10% Accurate timer (maximum)
Factory programmed: 1 msec to 100 sec
Factory programmed or user-programmable reset
delay
±10% Accurate timer (maximum)
Factory programmed option: 2 msec to 10 sec
Input voltage range: VDD = 1.04 V to
6.0 V
Fixed threshold voltage (VIT-): 1.05 V
to 5.4 V
Threshold voltage available in 50 mV steps
1.2% Voltage threshold accuracy (maximum)
Built-in hysteresis (VHYS): 5%
(typical)
Ultra low supply current: IDD = 250 nA
(typical)
Open-drain, push-pull; active-low outputs
Various programmability options:
Watchdog enable-disable
Watchdog startup delay: no delay to 10 sec
On
the fly timer extension: 1X to 256X
Latched output option
MR functionality
support
AEC-Q100 qualified with the following results:
Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Factory programmed or user-programmable watchdog
timeout
±10% Accurate timer (maximum)
Factory programmed: 1 msec to 100 sec
Factory programmed or user-programmable reset
delay
±10% Accurate timer (maximum)
Factory programmed option: 2 msec to 10 sec
Input voltage range: VDD = 1.04 V to
6.0 V
Fixed threshold voltage (VIT-): 1.05 V
to 5.4 V
Threshold voltage available in 50 mV steps
1.2% Voltage threshold accuracy (maximum)
Built-in hysteresis (VHYS): 5%
(typical)
Ultra low supply current: IDD = 250 nA
(typical)
Open-drain, push-pull; active-low outputs
Various programmability options:
Watchdog enable-disable
Watchdog startup delay: no delay to 10 sec
On
the fly timer extension: 1X to 256X
Latched output option
MR functionality
support
AEC-Q100 qualified with the following results:
Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Device temperature grade 1: –40°C to 125°C
ambient operating temperature range
Device temperature grade 1: –40°C to 125°C
ambient operating temperature rangeFactory programmed or user-programmable watchdog
timeout
±10% Accurate timer (maximum)
Factory programmed: 1 msec to 100 sec
±10% Accurate timer (maximum)
Factory programmed: 1 msec to 100 sec
±10% Accurate timer (maximum)Factory programmed: 1 msec to 100 secFactory programmed or user-programmable reset
delay
±10% Accurate timer (maximum)
Factory programmed option: 2 msec to 10 sec
±10% Accurate timer (maximum)
Factory programmed option: 2 msec to 10 sec
±10% Accurate timer (maximum)Factory programmed option: 2 msec to 10 secInput voltage range: VDD = 1.04 V to
6.0 VDDFixed threshold voltage (VIT-): 1.05 V
to 5.4 V
Threshold voltage available in 50 mV steps
1.2% Voltage threshold accuracy (maximum)
Built-in hysteresis (VHYS): 5%
(typical)
IT-
Threshold voltage available in 50 mV steps
1.2% Voltage threshold accuracy (maximum)
Built-in hysteresis (VHYS): 5%
(typical)
Threshold voltage available in 50 mV steps1.2% Voltage threshold accuracy (maximum)Built-in hysteresis (VHYS): 5%
(typical)HYSUltra low supply current: IDD = 250 nA
(typical)DDOpen-drain, push-pull; active-low outputsVarious programmability options:
Watchdog enable-disable
Watchdog startup delay: no delay to 10 sec
On
the fly timer extension: 1X to 256X
Latched output option
Watchdog enable-disable
Watchdog startup delay: no delay to 10 sec
On
the fly timer extension: 1X to 256X
Latched output option
Watchdog enable-disableWatchdog startup delay: no delay to 10 secOn
the fly timer extension: 1X to 256XLatched output option
MR functionality
supportMR
Applications
On-board (OBC) and
wireless charger
Driver
monitoring
Battery Management
System (BMS)
Front
camera
Surround view
system ECU
Applications
On-board (OBC) and
wireless charger
Driver
monitoring
Battery Management
System (BMS)
Front
camera
Surround view
system ECU
On-board (OBC) and
wireless charger
Driver
monitoring
Battery Management
System (BMS)
Front
camera
Surround view
system ECU
On-board (OBC) and
wireless charger
Driver
monitoring
Battery Management
System (BMS)
Front
camera
Surround view
system ECU
On-board (OBC) and
wireless charger
On-board (OBC) and
wireless charger
Driver
monitoring
Driver
monitoring
Battery Management
System (BMS)
Battery Management
System (BMS)
Front
camera
Front
camera
Surround view
system ECU
Surround view
system ECU
Description
The TPS35-Q1 is an ultra-low
power consumption (250 nA typical) device offering a precision voltage supervisor with a programmable timeout watchdog timer. The TPS35-Q1 supports wide threshold levels for undervoltage
supervision with 1.2% accuracy across the specified temperature range.
The TPS35-Q1 offers a high accuracy timeout watchdog timer with a host
of features for a wide variety of applications. The timeout watchdog timer can be
factory programmed or user programmed using an external capacitor. The timer value
can be changed on-the-fly using a combination of logic pins. The watchdog also
offers unique features such as enable-disable, start-up delay, independent WDO pin
option.
The
RESET or
WDO delay can be
set by factory-programmed default delay settings or programmed by an external
capacitor. The device also offers a latched
output operation where the output is latched until the supervisor or watchdog fault is cleared.
The TPS35-Q1 provides a
performance upgrade alternative to
TPS3851-Q1
device family. The TPS35-Q1 is available in a small 8-pin SOT-23 package.
Device Information
PART NUMBER
PACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
BODY SIZE (NOM)
TPS35-Q1
DDF (8)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application Circuit
Description
The TPS35-Q1 is an ultra-low
power consumption (250 nA typical) device offering a precision voltage supervisor with a programmable timeout watchdog timer. The TPS35-Q1 supports wide threshold levels for undervoltage
supervision with 1.2% accuracy across the specified temperature range.
The TPS35-Q1 offers a high accuracy timeout watchdog timer with a host
of features for a wide variety of applications. The timeout watchdog timer can be
factory programmed or user programmed using an external capacitor. The timer value
can be changed on-the-fly using a combination of logic pins. The watchdog also
offers unique features such as enable-disable, start-up delay, independent WDO pin
option.
The
RESET or
WDO delay can be
set by factory-programmed default delay settings or programmed by an external
capacitor. The device also offers a latched
output operation where the output is latched until the supervisor or watchdog fault is cleared.
The TPS35-Q1 provides a
performance upgrade alternative to
TPS3851-Q1
device family. The TPS35-Q1 is available in a small 8-pin SOT-23 package.
Device Information
PART NUMBER
PACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
BODY SIZE (NOM)
TPS35-Q1
DDF (8)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application Circuit
The TPS35-Q1 is an ultra-low
power consumption (250 nA typical) device offering a precision voltage supervisor with a programmable timeout watchdog timer. The TPS35-Q1 supports wide threshold levels for undervoltage
supervision with 1.2% accuracy across the specified temperature range.
The TPS35-Q1 offers a high accuracy timeout watchdog timer with a host
of features for a wide variety of applications. The timeout watchdog timer can be
factory programmed or user programmed using an external capacitor. The timer value
can be changed on-the-fly using a combination of logic pins. The watchdog also
offers unique features such as enable-disable, start-up delay, independent WDO pin
option.
The
RESET or
WDO delay can be
set by factory-programmed default delay settings or programmed by an external
capacitor. The device also offers a latched
output operation where the output is latched until the supervisor or watchdog fault is cleared.
The TPS35-Q1 provides a
performance upgrade alternative to
TPS3851-Q1
device family. The TPS35-Q1 is available in a small 8-pin SOT-23 package.
Device Information
PART NUMBER
PACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
BODY SIZE (NOM)
TPS35-Q1
DDF (8)
2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at the end of the data sheet.
The TPS35-Q1 is an ultra-low
power consumption (250 nA typical) device offering a precision voltage supervisor with a programmable timeout watchdog timer. The TPS35-Q1 supports wide threshold levels for undervoltage
supervision with 1.2% accuracy across the specified temperature range.
TPS35-Q1a precision voltage supervisor with timeout The TPS35-Q1 supports wide threshold levels for undervoltage
supervision with 1.2% accuracy across the specified temperature range.TPS35-Q1The TPS35-Q1 offers a high accuracy timeout watchdog timer with a host
of features for a wide variety of applications. The timeout watchdog timer can be
factory programmed or user programmed using an external capacitor. The timer value
can be changed on-the-fly using a combination of logic pins. The watchdog also
offers unique features such as enable-disable, start-up delay, independent WDO pin
option.TPS35-Q1The
RESET or
WDO delay can be
set by factory-programmed default delay settings or programmed by an external
capacitor. The device also offers a latched
output operation where the output is latched until the supervisor or watchdog fault is cleared.
RESET or RESETWDOsupervisor or The TPS35-Q1 provides a
performance upgrade alternative to
TPS3851-Q1
device family. The TPS35-Q1 is available in a small 8-pin SOT-23 package.TPS35-Q1
TPS3851-Q1
TPS3851-Q1TPS35-Q1
Device Information
PART NUMBER
PACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
BODY SIZE (NOM)
TPS35-Q1
DDF (8)
2.90 mm × 1.60 mm
Device Information
PART NUMBER
PACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
BODY SIZE (NOM)
TPS35-Q1
DDF (8)
2.90 mm × 1.60 mm
PART NUMBER
PACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
BODY SIZE (NOM)
PART NUMBER
PACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
BODY SIZE (NOM)
PART NUMBERPACKAGE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTE
#GUID-A90FCBEA-9211-41EC-A530-F55740F95637/DEVINFONOTEBODY SIZE (NOM)
TPS35-Q1
DDF (8)
2.90 mm × 1.60 mm
TPS35-Q1
DDF (8)
2.90 mm × 1.60 mm
TPS35-Q1
TPS35-Q1DDF (8)2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at the end of the data sheet.
For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application Circuit
Typical Application Circuit
Typical Application Circuit
Typical Application Circuit
Table of Contents
yes
Table of Contents
yes
yes
yes
Revision History
yes
November 2022
June 2023
*
A
Revision History
yes
November 2022
June 2023
*
A
yes
November 2022
June 2023
*
A
yesNovember 2022June 2023*A
Device Comparison
shows the device naming nomenclature of the TPS35-Q1. For all possible output types, threshold voltage options, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options.
Device Naming
Nomenclature
TPS35-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in .
Pin Compatible Device Families
DEVICE
VOLTAGE SUPERVISOR
TYPE OF WATCHDOG
TPS35-Q1
Yes
Timeout
TPS36-Q1
Yes
Window
TPS3435-Q1
No
Timeout
TPS3436-Q1
No
Window
Device Comparison
shows the device naming nomenclature of the TPS35-Q1. For all possible output types, threshold voltage options, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options.
Device Naming
Nomenclature
TPS35-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in .
Pin Compatible Device Families
DEVICE
VOLTAGE SUPERVISOR
TYPE OF WATCHDOG
TPS35-Q1
Yes
Timeout
TPS36-Q1
Yes
Window
TPS3435-Q1
No
Timeout
TPS3436-Q1
No
Window
shows the device naming nomenclature of the TPS35-Q1. For all possible output types, threshold voltage options, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options.
Device Naming
Nomenclature
TPS35-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in .
Pin Compatible Device Families
DEVICE
VOLTAGE SUPERVISOR
TYPE OF WATCHDOG
TPS35-Q1
Yes
Timeout
TPS36-Q1
Yes
Window
TPS3435-Q1
No
Timeout
TPS3436-Q1
No
Window
shows the device naming nomenclature of the TPS35-Q1. For all possible output types, threshold voltage options, watchdog time options and output assert delay options, see for more details. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options.TPS35-Q1threshold voltage options, E2E forum
Device Naming
Nomenclature
Device Naming
Nomenclature
TPS35-Q1 belongs to family of pin compatible devices offering different feature sets as highlighted in .TPS35-Q1
Pin Compatible Device Families
DEVICE
VOLTAGE SUPERVISOR
TYPE OF WATCHDOG
TPS35-Q1
Yes
Timeout
TPS36-Q1
Yes
Window
TPS3435-Q1
No
Timeout
TPS3436-Q1
No
Window
Pin Compatible Device Families
DEVICE
VOLTAGE SUPERVISOR
TYPE OF WATCHDOG
TPS35-Q1
Yes
Timeout
TPS36-Q1
Yes
Window
TPS3435-Q1
No
Timeout
TPS3436-Q1
No
Window
DEVICE
VOLTAGE SUPERVISOR
TYPE OF WATCHDOG
DEVICE
VOLTAGE SUPERVISOR
TYPE OF WATCHDOG
DEVICEVOLTAGE SUPERVISORTYPE OF WATCHDOG
TPS35-Q1
Yes
Timeout
TPS36-Q1
Yes
Window
TPS3435-Q1
No
Timeout
TPS3436-Q1
No
Window
TPS35-Q1
Yes
Timeout
TPS35-Q1
TPS35-Q1
TPS35-Q1YesTimeout
TPS36-Q1
Yes
Window
TPS36-Q1
TPS36-Q1
TPS36-Q1YesWindow
TPS3435-Q1
No
Timeout
TPS3435-Q1
TPS3435-Q1
TPS3435-Q1NoTimeout
TPS3436-Q1
No
Window
TPS3436-Q1
TPS3436-Q1
TPS3436-Q1NoWindow
Pin Configuration and Functions
Pin Configuration Option
A
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
B
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
C
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
D
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Functions
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
PINOUT A
PINOUT B
PINOUT C
PINOUT D
CRST
3
3
—
—
I
Programmable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CWD
2
2
—
—
I
Programmable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.
GND
4
4
4
4
—
Ground pin
MR
1
—
2
—
I
Manual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.
RESET
7
7
7
7
O
Reset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.
SET0
5
1
1
1
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET1
—
5
5
5
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
VDD
8
8
8
8
I
Supply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
WD-EN
—
—
6
2
I
Logic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WDI
6
6
3
3
I
Watchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.
WDO
—
—
—
6
O
Watchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.
Pin Configuration and Functions
Pin Configuration Option
A
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
B
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
C
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
D
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Functions
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
PINOUT A
PINOUT B
PINOUT C
PINOUT D
CRST
3
3
—
—
I
Programmable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CWD
2
2
—
—
I
Programmable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.
GND
4
4
4
4
—
Ground pin
MR
1
—
2
—
I
Manual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.
RESET
7
7
7
7
O
Reset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.
SET0
5
1
1
1
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET1
—
5
5
5
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
VDD
8
8
8
8
I
Supply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
WD-EN
—
—
6
2
I
Logic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WDI
6
6
3
3
I
Watchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.
WDO
—
—
—
6
O
Watchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.
Pin Configuration Option
A
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
B
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
C
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
D
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Functions
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
PINOUT A
PINOUT B
PINOUT C
PINOUT D
CRST
3
3
—
—
I
Programmable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CWD
2
2
—
—
I
Programmable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.
GND
4
4
4
4
—
Ground pin
MR
1
—
2
—
I
Manual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.
RESET
7
7
7
7
O
Reset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.
SET0
5
1
1
1
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET1
—
5
5
5
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
VDD
8
8
8
8
I
Supply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
WD-EN
—
—
6
2
I
Logic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WDI
6
6
3
3
I
Watchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.
WDO
—
—
—
6
O
Watchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.
Pin Configuration Option
A
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
B
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
C
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
D
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
A
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
A
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top ViewTPS35-Q1
Pin Configuration Option
B
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
B
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top ViewTPS35-Q1
Pin Configuration Option
C
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
C
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top ViewTPS35-Q1
Pin Configuration Option
D
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
Pin Configuration Option
D
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top View
DDF Package,
8-Pin SOT-23,
TPS35-Q1 Top ViewTPS35-Q1
Pin Functions
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
PINOUT A
PINOUT B
PINOUT C
PINOUT D
CRST
3
3
—
—
I
Programmable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CWD
2
2
—
—
I
Programmable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.
GND
4
4
4
4
—
Ground pin
MR
1
—
2
—
I
Manual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.
RESET
7
7
7
7
O
Reset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.
SET0
5
1
1
1
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET1
—
5
5
5
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
VDD
8
8
8
8
I
Supply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
WD-EN
—
—
6
2
I
Logic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WDI
6
6
3
3
I
Watchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.
WDO
—
—
—
6
O
Watchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.
Pin Functions
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
PINOUT A
PINOUT B
PINOUT C
PINOUT D
CRST
3
3
—
—
I
Programmable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CWD
2
2
—
—
I
Programmable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.
GND
4
4
4
4
—
Ground pin
MR
1
—
2
—
I
Manual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.
RESET
7
7
7
7
O
Reset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.
SET0
5
1
1
1
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET1
—
5
5
5
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
VDD
8
8
8
8
I
Supply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
WD-EN
—
—
6
2
I
Logic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WDI
6
6
3
3
I
Watchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.
WDO
—
—
—
6
O
Watchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
PINOUT A
PINOUT B
PINOUT C
PINOUT D
PIN NAME
PIN NUMBER
I/O
DESCRIPTION
PIN NAMEPIN NUMBERI/ODESCRIPTION
PINOUT A
PINOUT B
PINOUT C
PINOUT D
PINOUT APINOUT BPINOUT CPINOUT D
CRST
3
3
—
—
I
Programmable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CWD
2
2
—
—
I
Programmable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.
GND
4
4
4
4
—
Ground pin
MR
1
—
2
—
I
Manual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.
RESET
7
7
7
7
O
Reset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.
SET0
5
1
1
1
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET1
—
5
5
5
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
VDD
8
8
8
8
I
Supply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
WD-EN
—
—
6
2
I
Logic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WDI
6
6
3
3
I
Watchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.
WDO
—
—
—
6
O
Watchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.
CRST
3
3
—
—
I
Programmable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CRST33——IProgrammable reset timeout pin.
Connect a capacitor between this pin and GND to program the reset
timeout period. See
for
more details.
CWD
2
2
—
—
I
Programmable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.
CWD22——IProgrammable watchdog timeout
input. Watchdog timeout is set by
connecting a capacitor between this pin and ground. See
for
more details.timeout
GND
4
4
4
4
—
Ground pin
GND4444—Ground pin
MR
1
—
2
—
I
Manual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.
MR
MR1—2—IManual reset pin. A logic low
on this pin asserts the RESET. See
for
more details.RESET
RESET
7
7
7
7
O
Reset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.
RESET
RESET7777OReset output. Connect
RESET to VDD using a pull up resistance
when using open drain output. RESET is asserted
when the voltage at the VDD pin goes below the undervoltage
threshold (VIT-) or MR pin is driven
LOW. For pinout options which do not support independent
WDO pin, RESET is also
asserted for watchdog error. See
for
more details.RESETRESETIT-MRWDORESET
SET0
5
1
1
1
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET05111ILogic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.timer scaling
SET1
—
5
5
5
I
Logic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.
SET1—555ILogic input. SET0, SET1, and
WD-EN pins select the watchdog timer scaling and enable-disable the watchdog; see
for
more details.timer scaling
VDD
8
8
8
8
I
Supply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
VDD8888ISupply voltage pin. For noisy
systems, connecting a 0.1-µF bypass capacitor is
recommended.
WD-EN
—
—
6
2
I
Logic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WD-EN——62ILogic input. Logic high input
enables the watchdog monitoring feature. See
for
more details.
WDI
6
6
3
3
I
Watchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.
WDI6633IWatchdog input. A falling
transition (edge) must occur at this pin before the timeout expires in
order for RESET / WDO to
not assert. See
for
more details.before the timeout expiresRESETWDO
WDO
—
—
—
6
O
Watchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.
WDO
WDO———6OWatchdog output. Connect
WDO to VDD using pull up resistance when
using open drain output. WDO asserts when a
watchdog error occurs. WDO only asserts when
RESET is high. When a watchdog error
occurs, WDO asserts for the set
RESET timeout delay (tD). When
RESET is asserted, WDO
is deasserted and watchdog functionality is disabled. See
for
more details.WDOWDOWDORESETWDORESETDRESETWDO
Specifications
Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1
MIN
MAX
UNIT
Voltage
VDD
–0.3
6.5
V
Voltage
CWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)
–0.3
VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
V
RESET (Open Drain),
WDO (Open Drain)
–0.3
6.5
Current
RESET,
WDO pin
–20
20
mA
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
Operating ambient temperature, TA
–40
125
℃
Temperature
Storage, Tstg
–65
150
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
±2000
V
Charged device model (CDM), per AEC Q100-011
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Voltage
VDD (Active Low output)
0.9
6
V
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
0
VDD
RESET
(Open Drain) ,
WDO (Open Drain)
0
6
RESET
(Open Drain) ,
WDO (Push Pull)
0
VDD
Current
RESET,
WDO pin current
–5
5
mA
CRST
CRST pin capacitor range
1.5
1800
nF
CWD
CWD pin capacitor range
1.5
1000
nF
TA
Operating ambient temperature
–40
125
℃
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
Thermal Information
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
UNIT
DDF (SOT23-8)
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
94.7
°C/W
RθJB
Junction-to-board thermal resistance
92.4
°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJB
Junction-to-board characterization parameter
91.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Electrical Characteristics
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
6
V
VIT–
Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
VIT– = 1.05 V to 1.95 V
–1.4
±0.5
1.4
%
VIT– = 2.0 V to 5.4 V
–1.2
±0.5
1.2
VHYS
Hysteresis VIT– pin
VIT– = 1.05 V to 5.4 V
3
5
7
%
IDD
Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
VDD = 2 VVIT– = 1.05 V to 1.95 V
TA = –40℃ to 85℃
0.25
0.8
µA
0.25
3
VDD = 6 VVIT– = 1.05 V to 5.4 V
TA = –40℃ to 85℃
0.25
0.8
0.25
3
VIL
Low level input voltage WD–EN, WDI, SETx, MR
(3)
0.3VDD
V
VIH
High level input voltage WD–EN, WDI, SETx, MR
(3)
0.7VDD
V
R
MR
Manual reset internal pull-up resistance
100
kΩ
RESET / WDO (Open-drain active-low)
VOL
Low level output voltage
VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
mV
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6VTA = –40℃ to 85℃
10
30
nA
VDD = VPULLUP = 6V
10
120
nA
RESET / WDO (Push-pull active-low)
VPOR
Power on RESET voltage (5)
VOL(max) = 300 mVIOUT(Sink) = 15 µA
900
mV
VOL
Low level output voltage
VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA
300
mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
VOH
High level output voltage
VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA
0.8VDD
V
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA
0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA
0.8VDD
VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
VPOR is the minimum VDD voltage level for a controlled output state
Timing Requirements
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tGI_VIT–
Glitch immunity VIT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
15
µs
t
MR_PW
MR pin pulse duration to assert reset
100
ns
tP-WD
WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
500
ns
tHD-WDEN
WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
200
µs
tHD-SETx
SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
150
µs
tWD
Watchdog timeout period
Orderable Option TPS35xxxxB
0.8
1
1.2
ms
Orderable Option TPS35xxxxC
4
5
6
Orderable Option TPS35xxxxD
9
10
11
Orderable Option TPS35xxxxE
18
20
22
Orderable Option TPS35xxxxF
45
50
55
Orderable Option TPS35xxxxG
90
100
110
Orderable Option TPS35xxxxH
180
200
220
Orderable Option TPS35xxxxI
0.9
1
1.1
s
Orderable Option TPS35xxxxJ
1.26
1.4
1.54
Orderable Option TPS35xxxxK
1.44
1.6
1.76
Orderable Option TPS35xxxxL
9
10
11
Orderable Option TPS35xxxxM
45
50
55
Orderable Option TPS35xxxxN
90
100
110
Overdrive % = [(VDD/ VIT–) – 1] × 100%
Not production tested
Switching Characteristics
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTRT
Startup delay(4)
500
µs
tP_HL
RESET detect delay for VDD falling below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
30
50
µs
tSD
Watchdog startup delay
Orderable part number TPS35xA, TPS35xG
0
ms
Orderable part number TPS35xB, TPS35xH
180
200
220
Orderable part number TPS35xC, TPS35xI
450
500
550
Orderable part number TPS35xD, TPS35xJ
0.9
1
1.1
s
Orderable part number TPS35xE, TPS35xK
4.5
5
5.5
Orderable part number TPS35xF, TPS35xL
9
10
11
tD
Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
Orderable part number TPS35xxxxxxB
1.6
2
2.4
ms
Orderable part number TPS35xxxxxxC
9
10
11
ms
Orderable part number TPS35xxxxxxD
22.5
25
27.5
ms
Orderable part number TPS35xxxxxxE
45
50
55
ms
Orderable part number TPS35xxxxxxF
90
100
110
ms
Orderable part number TPS35xxxxxxG
180
200
220
ms
Orderable part number TPS35xxxxxxH
0.9
1
1.1
s
Orderable part number TPS35xxxxxxI
9
10
11
s
tWDO
Watchdog timeout delay
tD
s
t
MR_RES
Propagation delay from MR low to reset assertion
VDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
100
ns
t
MR_tD
Delay from MR release to reset deassert
VDD = 3.3 V,
MR = V
MR_L to V
MR_H
tD
s
tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay.
VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)
Timing Diagrams
*
Added a footnote to for tINIT
no
Functional Timing Diagram
Typical Characteristics
all curves are taken at TA = 25°C
(unless otherwise noted)
VIT-
Accuracy vs Temperature
VIT-
Accuracy Histogram
VIT- Hysteresis Vs Temperature
Supply Glitch
Immunity vs Overdrive
Timer Accuracy vs
Temperature
Timer Accuracy Histogram
tWD vs Capacitance
tD vs Capacitance
RESET VOL vs I
sink, VDD = 1.5 V
WDO VOL vs I
sink, VDD = 1.5 V
RESET VOL vs I sink, VDD = 3.3 V
WDO VOL vs I sink, VDD = 3.3 V
RESET VOH vs I source, VDD = 2.0 V
WDO VOH vs I source, VDD = 2.0 V
RESET VOH vs I source, VDD = 6.0 V
WDO VOH vs I source, VDD = 6.0 V
Supply Current
vs Power-Supply Voltage
Specifications
Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1
MIN
MAX
UNIT
Voltage
VDD
–0.3
6.5
V
Voltage
CWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)
–0.3
VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
V
RESET (Open Drain),
WDO (Open Drain)
–0.3
6.5
Current
RESET,
WDO pin
–20
20
mA
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
Operating ambient temperature, TA
–40
125
℃
Temperature
Storage, Tstg
–65
150
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1
MIN
MAX
UNIT
Voltage
VDD
–0.3
6.5
V
Voltage
CWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)
–0.3
VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
V
RESET (Open Drain),
WDO (Open Drain)
–0.3
6.5
Current
RESET,
WDO pin
–20
20
mA
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
Operating ambient temperature, TA
–40
125
℃
Temperature
Storage, Tstg
–65
150
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1
MIN
MAX
UNIT
Voltage
VDD
–0.3
6.5
V
Voltage
CWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)
–0.3
VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
V
RESET (Open Drain),
WDO (Open Drain)
–0.3
6.5
Current
RESET,
WDO pin
–20
20
mA
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
Operating ambient temperature, TA
–40
125
℃
Temperature
Storage, Tstg
–65
150
over operating free-air temperature range, unless otherwise noted#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER1
MIN
MAX
UNIT
Voltage
VDD
–0.3
6.5
V
Voltage
CWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)
–0.3
VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
V
RESET (Open Drain),
WDO (Open Drain)
–0.3
6.5
Current
RESET,
WDO pin
–20
20
mA
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
Operating ambient temperature, TA
–40
125
℃
Temperature
Storage, Tstg
–65
150
MIN
MAX
UNIT
MIN
MAX
UNIT
MINMAXUNIT
Voltage
VDD
–0.3
6.5
V
Voltage
CWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)
–0.3
VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
V
RESET (Open Drain),
WDO (Open Drain)
–0.3
6.5
Current
RESET,
WDO pin
–20
20
mA
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
Operating ambient temperature, TA
–40
125
℃
Temperature
Storage, Tstg
–65
150
Voltage
VDD
–0.3
6.5
V
VoltageVDD–0.36.5V
Voltage
CWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)
–0.3
VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
V
VoltageCWD, CRST, WD–EN, SETx, WDI, MR
(2), RESET (Push Pull),
WDO (Push Pull)WDRSTMR(2) RESET (Push Pull),RESETWDO–0.3VDD+0.3 #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1
DD#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/SF_WMY9TRSL1V
RESET (Open Drain),
WDO (Open Drain)
–0.3
6.5
RESET (Open Drain),
WDO (Open Drain)
RESET (Open Drain), RESET
WDO (Open Drain)WDO–0.36.5
Current
RESET,
WDO pin
–20
20
mA
Current
RESET,
WDO pin
RESET,
RESET,WDO–2020mA
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
Operating ambient temperature, TA
–40
125
℃
Temperature #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244046/A_SUPERVISOR_VVCM_1_ABSMAX_FOOTER2Operating ambient temperature, TA
A–40125℃
Temperature
Storage, Tstg
–65
150
TemperatureStorage, Tstg
stg–65150
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
The absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smaller
As a result of the low dissipated power in this device, it is assumed that TJ = TA.
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.Absolute Maximum RatingRecommended Operating ConditionIf the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. MRDDDDMRThe absolute maximum rating is (VDD + 0.3) V or 6.5 V, whichever is smallerAs a result of the low dissipated power in this device, it is assumed that TJ = TA.JA
ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
±2000
V
Charged device model (CDM), per AEC Q100-011
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
±2000
V
Charged device model (CDM), per AEC Q100-011
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
±2000
V
Charged device model (CDM), per AEC Q100-011
±750
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
±2000
V
Charged device model (CDM), per AEC Q100-011
±750
VALUE
UNIT
VALUE
UNIT
VALUEUNIT
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
±2000
V
Charged device model (CDM), per AEC Q100-011
±750
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
±2000
V
V(ESD)
(ESD)Electrostatic dischargeHuman body model (HBM), per AEC Q100-002#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244048/A_SUPERVISOR_VVCM_3_ESD_RATINGS_AUTOMOTIVE_FOOTER1±2000V
Charged device model (CDM), per AEC Q100-011
±750
Charged device model (CDM), per AEC Q100-011±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Voltage
VDD (Active Low output)
0.9
6
V
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
0
VDD
RESET
(Open Drain) ,
WDO (Open Drain)
0
6
RESET
(Open Drain) ,
WDO (Push Pull)
0
VDD
Current
RESET,
WDO pin current
–5
5
mA
CRST
CRST pin capacitor range
1.5
1800
nF
CWD
CWD pin capacitor range
1.5
1000
nF
TA
Operating ambient temperature
–40
125
℃
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Voltage
VDD (Active Low output)
0.9
6
V
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
0
VDD
RESET
(Open Drain) ,
WDO (Open Drain)
0
6
RESET
(Open Drain) ,
WDO (Push Pull)
0
VDD
Current
RESET,
WDO pin current
–5
5
mA
CRST
CRST pin capacitor range
1.5
1800
nF
CWD
CWD pin capacitor range
1.5
1000
nF
TA
Operating ambient temperature
–40
125
℃
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Voltage
VDD (Active Low output)
0.9
6
V
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
0
VDD
RESET
(Open Drain) ,
WDO (Open Drain)
0
6
RESET
(Open Drain) ,
WDO (Push Pull)
0
VDD
Current
RESET,
WDO pin current
–5
5
mA
CRST
CRST pin capacitor range
1.5
1800
nF
CWD
CWD pin capacitor range
1.5
1000
nF
TA
Operating ambient temperature
–40
125
℃
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
Voltage
VDD (Active Low output)
0.9
6
V
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
0
VDD
RESET
(Open Drain) ,
WDO (Open Drain)
0
6
RESET
(Open Drain) ,
WDO (Push Pull)
0
VDD
Current
RESET,
WDO pin current
–5
5
mA
CRST
CRST pin capacitor range
1.5
1800
nF
CWD
CWD pin capacitor range
1.5
1000
nF
TA
Operating ambient temperature
–40
125
℃
MIN
NOM
MAX
UNIT
MIN
NOM
MAX
UNIT
MINNOMMAXUNIT
Voltage
VDD (Active Low output)
0.9
6
V
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
0
VDD
RESET
(Open Drain) ,
WDO (Open Drain)
0
6
RESET
(Open Drain) ,
WDO (Push Pull)
0
VDD
Current
RESET,
WDO pin current
–5
5
mA
CRST
CRST pin capacitor range
1.5
1800
nF
CWD
CWD pin capacitor range
1.5
1000
nF
TA
Operating ambient temperature
–40
125
℃
Voltage
VDD (Active Low output)
0.9
6
V
VoltageVDD (Active Low output)0.96V
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
0
VDD
CWD, CRST, WD–EN, SETx, WDI, MR
(1)
WDRSTMR(1)0VDD
RESET
(Open Drain) ,
WDO (Open Drain)
0
6
RESET
(Open Drain) ,
WDO (Open Drain)
RESET
RESET (Open Drain) ,WDO06
RESET
(Open Drain) ,
WDO (Push Pull)
0
VDD
RESET
(Open Drain) ,
WDO (Push Pull)
RESET
RESET(Open Drain) ,WDO0VDD
Current
RESET,
WDO pin current
–5
5
mA
Current
RESET,
WDO pin current
RESET,RESETWDO–55mA
CRST
CRST pin capacitor range
1.5
1800
nF
CRST
RSTCRST pin capacitor rangeRST1.51800nF
CWD
CWD pin capacitor range
1.5
1000
nF
CWD
WDCWD pin capacitor rangeWD1.51000nF
TA
Operating ambient temperature
–40
125
℃
TA
AOperating ambient temperature–40125℃
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR. VMR should not be higher than VDD.
MRDDDDMRMRDD.
Thermal Information
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
UNIT
DDF (SOT23-8)
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
94.7
°C/W
RθJB
Junction-to-board thermal resistance
92.4
°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJB
Junction-to-board characterization parameter
91.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
Thermal Information
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
UNIT
DDF (SOT23-8)
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
94.7
°C/W
RθJB
Junction-to-board thermal resistance
92.4
°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJB
Junction-to-board characterization parameter
91.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
UNIT
DDF (SOT23-8)
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
94.7
°C/W
RθJB
Junction-to-board thermal resistance
92.4
°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJB
Junction-to-board characterization parameter
91.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
UNIT
DDF (SOT23-8)
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
94.7
°C/W
RθJB
Junction-to-board thermal resistance
92.4
°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJB
Junction-to-board characterization parameter
91.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
UNIT
DDF (SOT23-8)
8 PINS
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
UNIT
THERMAL METRIC#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244050/A_SUPERVISOR_VVCM_5_THERMAL_FOOTER1
TPS35-Q1
TPS35-Q1UNIT
DDF (SOT23-8)
DDF (SOT23-8)
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
175.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
94.7
°C/W
RθJB
Junction-to-board thermal resistance
92.4
°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJB
Junction-to-board characterization parameter
91.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
RθJA
Junction-to-ambient thermal resistance
175.3
°C/W
RθJA
θJAJunction-to-ambient thermal resistance175.3°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
94.7
°C/W
RθJC(top)
θJC(top)Junction-to-case (top) thermal resistance94.7°C/W
RθJB
Junction-to-board thermal resistance
92.4
°C/W
RθJB
θJBJunction-to-board thermal resistance92.4°C/W
ψJT
Junction-to-top characterization parameter
8.4
°C/W
ψJT
JTJunction-to-top characterization parameter8.4°C/W
ψJB
Junction-to-board characterization parameter
91.9
°C/W
ψJB
JBJunction-to-board characterization parameter91.9°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
RθJC(bot)
θJC(bot)Junction-to-case (bottom) thermal resistanceN/A°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.Semiconductor and IC Package Thermal Metrics
Electrical Characteristics
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
6
V
VIT–
Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
VIT– = 1.05 V to 1.95 V
–1.4
±0.5
1.4
%
VIT– = 2.0 V to 5.4 V
–1.2
±0.5
1.2
VHYS
Hysteresis VIT– pin
VIT– = 1.05 V to 5.4 V
3
5
7
%
IDD
Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
VDD = 2 VVIT– = 1.05 V to 1.95 V
TA = –40℃ to 85℃
0.25
0.8
µA
0.25
3
VDD = 6 VVIT– = 1.05 V to 5.4 V
TA = –40℃ to 85℃
0.25
0.8
0.25
3
VIL
Low level input voltage WD–EN, WDI, SETx, MR
(3)
0.3VDD
V
VIH
High level input voltage WD–EN, WDI, SETx, MR
(3)
0.7VDD
V
R
MR
Manual reset internal pull-up resistance
100
kΩ
RESET / WDO (Open-drain active-low)
VOL
Low level output voltage
VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
mV
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6VTA = –40℃ to 85℃
10
30
nA
VDD = VPULLUP = 6V
10
120
nA
RESET / WDO (Push-pull active-low)
VPOR
Power on RESET voltage (5)
VOL(max) = 300 mVIOUT(Sink) = 15 µA
900
mV
VOL
Low level output voltage
VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA
300
mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
VOH
High level output voltage
VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA
0.8VDD
V
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA
0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA
0.8VDD
VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
VPOR is the minimum VDD voltage level for a controlled output state
Electrical Characteristics
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
6
V
VIT–
Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
VIT– = 1.05 V to 1.95 V
–1.4
±0.5
1.4
%
VIT– = 2.0 V to 5.4 V
–1.2
±0.5
1.2
VHYS
Hysteresis VIT– pin
VIT– = 1.05 V to 5.4 V
3
5
7
%
IDD
Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
VDD = 2 VVIT– = 1.05 V to 1.95 V
TA = –40℃ to 85℃
0.25
0.8
µA
0.25
3
VDD = 6 VVIT– = 1.05 V to 5.4 V
TA = –40℃ to 85℃
0.25
0.8
0.25
3
VIL
Low level input voltage WD–EN, WDI, SETx, MR
(3)
0.3VDD
V
VIH
High level input voltage WD–EN, WDI, SETx, MR
(3)
0.7VDD
V
R
MR
Manual reset internal pull-up resistance
100
kΩ
RESET / WDO (Open-drain active-low)
VOL
Low level output voltage
VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
mV
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6VTA = –40℃ to 85℃
10
30
nA
VDD = VPULLUP = 6V
10
120
nA
RESET / WDO (Push-pull active-low)
VPOR
Power on RESET voltage (5)
VOL(max) = 300 mVIOUT(Sink) = 15 µA
900
mV
VOL
Low level output voltage
VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA
300
mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
VOH
High level output voltage
VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA
0.8VDD
V
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA
0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA
0.8VDD
VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
VPOR is the minimum VDD voltage level for a controlled output state
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
6
V
VIT–
Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
VIT– = 1.05 V to 1.95 V
–1.4
±0.5
1.4
%
VIT– = 2.0 V to 5.4 V
–1.2
±0.5
1.2
VHYS
Hysteresis VIT– pin
VIT– = 1.05 V to 5.4 V
3
5
7
%
IDD
Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
VDD = 2 VVIT– = 1.05 V to 1.95 V
TA = –40℃ to 85℃
0.25
0.8
µA
0.25
3
VDD = 6 VVIT– = 1.05 V to 5.4 V
TA = –40℃ to 85℃
0.25
0.8
0.25
3
VIL
Low level input voltage WD–EN, WDI, SETx, MR
(3)
0.3VDD
V
VIH
High level input voltage WD–EN, WDI, SETx, MR
(3)
0.7VDD
V
R
MR
Manual reset internal pull-up resistance
100
kΩ
RESET / WDO (Open-drain active-low)
VOL
Low level output voltage
VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
mV
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6VTA = –40℃ to 85℃
10
30
nA
VDD = VPULLUP = 6V
10
120
nA
RESET / WDO (Push-pull active-low)
VPOR
Power on RESET voltage (5)
VOL(max) = 300 mVIOUT(Sink) = 15 µA
900
mV
VOL
Low level output voltage
VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA
300
mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
VOH
High level output voltage
VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA
0.8VDD
V
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA
0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA
0.8VDD
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR RESETpull-upWDOpull-upLOADA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
6
V
VIT–
Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
VIT– = 1.05 V to 1.95 V
–1.4
±0.5
1.4
%
VIT– = 2.0 V to 5.4 V
–1.2
±0.5
1.2
VHYS
Hysteresis VIT– pin
VIT– = 1.05 V to 5.4 V
3
5
7
%
IDD
Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
VDD = 2 VVIT– = 1.05 V to 1.95 V
TA = –40℃ to 85℃
0.25
0.8
µA
0.25
3
VDD = 6 VVIT– = 1.05 V to 5.4 V
TA = –40℃ to 85℃
0.25
0.8
0.25
3
VIL
Low level input voltage WD–EN, WDI, SETx, MR
(3)
0.3VDD
V
VIH
High level input voltage WD–EN, WDI, SETx, MR
(3)
0.7VDD
V
R
MR
Manual reset internal pull-up resistance
100
kΩ
RESET / WDO (Open-drain active-low)
VOL
Low level output voltage
VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
mV
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6VTA = –40℃ to 85℃
10
30
nA
VDD = VPULLUP = 6V
10
120
nA
RESET / WDO (Push-pull active-low)
VPOR
Power on RESET voltage (5)
VOL(max) = 300 mVIOUT(Sink) = 15 µA
900
mV
VOL
Low level output voltage
VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA
300
mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
VOH
High level output voltage
VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA
0.8VDD
V
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA
0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA
0.8VDD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
6
V
VIT–
Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
VIT– = 1.05 V to 1.95 V
–1.4
±0.5
1.4
%
VIT– = 2.0 V to 5.4 V
–1.2
±0.5
1.2
VHYS
Hysteresis VIT– pin
VIT– = 1.05 V to 5.4 V
3
5
7
%
IDD
Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
VDD = 2 VVIT– = 1.05 V to 1.95 V
TA = –40℃ to 85℃
0.25
0.8
µA
0.25
3
VDD = 6 VVIT– = 1.05 V to 5.4 V
TA = –40℃ to 85℃
0.25
0.8
0.25
3
VIL
Low level input voltage WD–EN, WDI, SETx, MR
(3)
0.3VDD
V
VIH
High level input voltage WD–EN, WDI, SETx, MR
(3)
0.7VDD
V
R
MR
Manual reset internal pull-up resistance
100
kΩ
RESET / WDO (Open-drain active-low)
VOL
Low level output voltage
VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
mV
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6VTA = –40℃ to 85℃
10
30
nA
VDD = VPULLUP = 6V
10
120
nA
RESET / WDO (Push-pull active-low)
VPOR
Power on RESET voltage (5)
VOL(max) = 300 mVIOUT(Sink) = 15 µA
900
mV
VOL
Low level output voltage
VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA
300
mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
VOH
High level output voltage
VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA
0.8VDD
V
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA
0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA
0.8VDD
COMMON PARAMETERS
COMMON PARAMETERS
VDD
Input supply voltage
Active LOW output
1.04
6
V
VDD
DDInput supply voltageActive LOW output1.046V
VIT–
Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
VIT– = 1.05 V to 1.95 V
–1.4
±0.5
1.4
%
VIT–
IT–Negative-going input threshold accuracy #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER1VIT– = 1.05 V to 1.95 VIT––1.4±0.51.4%
VIT– = 2.0 V to 5.4 V
–1.2
±0.5
1.2
VIT– = 2.0 V to 5.4 VIT––1.2±0.51.2
VHYS
Hysteresis VIT– pin
VIT– = 1.05 V to 5.4 V
3
5
7
%
VHYS
HYSHysteresis VIT– pinIT–VIT– = 1.05 V to 5.4 VIT–357%
IDD
Supply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
VDD = 2 VVIT– = 1.05 V to 1.95 V
TA = –40℃ to 85℃
0.25
0.8
µA
IDD
DDSupply current into VDD pin #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244051/A_SUPERVISOR_VVCM_6_ELECTCHAR_FOOTER5VDD = 2 VVIT– = 1.05 V to 1.95 VDDIT–TA = –40℃ to 85℃ A0.250.8µA
0.25
3
0.253
VDD = 6 VVIT– = 1.05 V to 5.4 V
TA = –40℃ to 85℃
0.25
0.8
VDD = 6 VVIT– = 1.05 V to 5.4 VDDIT–TA = –40℃ to 85℃ A0.250.8
0.25
3
0.253
VIL
Low level input voltage WD–EN, WDI, SETx, MR
(3)
0.3VDD
V
VIL
ILLow level input voltage WD–EN, WDI, SETx, MR
(3)
MR(3)0.3VDD
DDV
VIH
High level input voltage WD–EN, WDI, SETx, MR
(3)
0.7VDD
V
VIH
IHHigh level input voltage WD–EN, WDI, SETx, MR
(3)
MR(3)0.7VDD
DDV
R
MR
Manual reset internal pull-up resistance
100
kΩ
R
MR
MR
MRManual reset internal pull-up resistance100kΩ
RESET / WDO (Open-drain active-low)
RESET / WDO (Open-drain active-low)RESETWDO
VOL
Low level output voltage
VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
mV
VOL
OLLow level output voltage VDD =1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µADDIT–OUT(Sink)300mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
mV
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mADDIT–OUT(Sink)300mV
Ilkg(OD)
Open-Drain output leakage current
VDD = VPULLUP = 6VTA = –40℃ to 85℃
10
30
nA
Ilkg(OD)
lkg(OD)Open-Drain output leakage currentVDD = VPULLUP = 6VTA = –40℃ to 85℃DDPULLUPA1030nA
VDD = VPULLUP = 6V
10
120
nA
VDD = VPULLUP = 6VDDPULLUP10120nA
RESET / WDO (Push-pull active-low)
RESET / WDO (Push-pull active-low)RESETWDO
VPOR
Power on RESET voltage (5)
VOL(max) = 300 mVIOUT(Sink) = 15 µA
900
mV
VPOR
PORPower on RESET voltage (5)
RESET(5)VOL(max) = 300 mVIOUT(Sink) = 15 µAOL(max)OUT(Sink)900mV
VOL
Low level output voltage
VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µA
300
mV
VOL
OLLow level output voltage VDD = 0.9 V, 1.05 V ≤ VIT– ≤ 1.5 VIOUT(Sink) = 15 µADDIT–OUT(Sink)300mV
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µA
300
VDD = 1.5 V, 1.55 V ≤ VIT– ≤ 3.35 VIOUT(Sink) = 500 µADDIT–OUT(Sink)300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mA
300
VDD = 3.3 V, 3.4 V ≤ VIT– ≤ 5.4 VIOUT(Sink) = 2 mADDIT–OUT(Sink)300
VOH
High level output voltage
VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µA
0.8VDD
V
VOH
OHHigh level output voltage VDD = 1.8 V, 1.05 V ≤ VIT– ≤ 1.4 VIOUT(Source) = 500 µADD IT–OUT(Source)0.8VDD
DDV
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µA
0.8VDD
VDD = 3.3 V, 1.45 V ≤ VIT– ≤ 3.0 VIOUT(Source) = 500 µADD IT–OUT(Source)0.8VDD
DD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mA
0.8VDD
VDD = 6 V, 3.05 V ≤ VIT– ≤ 5.4 VIOUT(Source) = 2 mADD IT–OUT(Source)0.8VDD
DD
VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.
If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.
VPOR is the minimum VDD voltage level for a controlled output state
VIT– threshold voltage range from 1.05 V to 5.4 V in 50 mV steps.IT–If the logic signal driving MR is less than VDD, then additional current flows into VDD and out of MR.MRDDDD MRVPOR is the minimum VDD voltage level for a controlled output statePORDD
Timing Requirements
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tGI_VIT–
Glitch immunity VIT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
15
µs
t
MR_PW
MR pin pulse duration to assert reset
100
ns
tP-WD
WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
500
ns
tHD-WDEN
WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
200
µs
tHD-SETx
SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
150
µs
tWD
Watchdog timeout period
Orderable Option TPS35xxxxB
0.8
1
1.2
ms
Orderable Option TPS35xxxxC
4
5
6
Orderable Option TPS35xxxxD
9
10
11
Orderable Option TPS35xxxxE
18
20
22
Orderable Option TPS35xxxxF
45
50
55
Orderable Option TPS35xxxxG
90
100
110
Orderable Option TPS35xxxxH
180
200
220
Orderable Option TPS35xxxxI
0.9
1
1.1
s
Orderable Option TPS35xxxxJ
1.26
1.4
1.54
Orderable Option TPS35xxxxK
1.44
1.6
1.76
Orderable Option TPS35xxxxL
9
10
11
Orderable Option TPS35xxxxM
45
50
55
Orderable Option TPS35xxxxN
90
100
110
Overdrive % = [(VDD/ VIT–) – 1] × 100%
Not production tested
Timing Requirements
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tGI_VIT–
Glitch immunity VIT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
15
µs
t
MR_PW
MR pin pulse duration to assert reset
100
ns
tP-WD
WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
500
ns
tHD-WDEN
WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
200
µs
tHD-SETx
SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
150
µs
tWD
Watchdog timeout period
Orderable Option TPS35xxxxB
0.8
1
1.2
ms
Orderable Option TPS35xxxxC
4
5
6
Orderable Option TPS35xxxxD
9
10
11
Orderable Option TPS35xxxxE
18
20
22
Orderable Option TPS35xxxxF
45
50
55
Orderable Option TPS35xxxxG
90
100
110
Orderable Option TPS35xxxxH
180
200
220
Orderable Option TPS35xxxxI
0.9
1
1.1
s
Orderable Option TPS35xxxxJ
1.26
1.4
1.54
Orderable Option TPS35xxxxK
1.44
1.6
1.76
Orderable Option TPS35xxxxL
9
10
11
Orderable Option TPS35xxxxM
45
50
55
Orderable Option TPS35xxxxN
90
100
110
Overdrive % = [(VDD/ VIT–) – 1] × 100%
Not production tested
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tGI_VIT–
Glitch immunity VIT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
15
µs
t
MR_PW
MR pin pulse duration to assert reset
100
ns
tP-WD
WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
500
ns
tHD-WDEN
WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
200
µs
tHD-SETx
SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
150
µs
tWD
Watchdog timeout period
Orderable Option TPS35xxxxB
0.8
1
1.2
ms
Orderable Option TPS35xxxxC
4
5
6
Orderable Option TPS35xxxxD
9
10
11
Orderable Option TPS35xxxxE
18
20
22
Orderable Option TPS35xxxxF
45
50
55
Orderable Option TPS35xxxxG
90
100
110
Orderable Option TPS35xxxxH
180
200
220
Orderable Option TPS35xxxxI
0.9
1
1.1
s
Orderable Option TPS35xxxxJ
1.26
1.4
1.54
Orderable Option TPS35xxxxK
1.44
1.6
1.76
Orderable Option TPS35xxxxL
9
10
11
Orderable Option TPS35xxxxM
45
50
55
Orderable Option TPS35xxxxN
90
100
110
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR RESETpull-upWDOpull-upLOADA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tGI_VIT–
Glitch immunity VIT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
15
µs
t
MR_PW
MR pin pulse duration to assert reset
100
ns
tP-WD
WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
500
ns
tHD-WDEN
WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
200
µs
tHD-SETx
SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
150
µs
tWD
Watchdog timeout period
Orderable Option TPS35xxxxB
0.8
1
1.2
ms
Orderable Option TPS35xxxxC
4
5
6
Orderable Option TPS35xxxxD
9
10
11
Orderable Option TPS35xxxxE
18
20
22
Orderable Option TPS35xxxxF
45
50
55
Orderable Option TPS35xxxxG
90
100
110
Orderable Option TPS35xxxxH
180
200
220
Orderable Option TPS35xxxxI
0.9
1
1.1
s
Orderable Option TPS35xxxxJ
1.26
1.4
1.54
Orderable Option TPS35xxxxK
1.44
1.6
1.76
Orderable Option TPS35xxxxL
9
10
11
Orderable Option TPS35xxxxM
45
50
55
Orderable Option TPS35xxxxN
90
100
110
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tGI_VIT–
Glitch immunity VIT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
15
µs
t
MR_PW
MR pin pulse duration to assert reset
100
ns
tP-WD
WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
500
ns
tHD-WDEN
WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
200
µs
tHD-SETx
SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
150
µs
tWD
Watchdog timeout period
Orderable Option TPS35xxxxB
0.8
1
1.2
ms
Orderable Option TPS35xxxxC
4
5
6
Orderable Option TPS35xxxxD
9
10
11
Orderable Option TPS35xxxxE
18
20
22
Orderable Option TPS35xxxxF
45
50
55
Orderable Option TPS35xxxxG
90
100
110
Orderable Option TPS35xxxxH
180
200
220
Orderable Option TPS35xxxxI
0.9
1
1.1
s
Orderable Option TPS35xxxxJ
1.26
1.4
1.54
Orderable Option TPS35xxxxK
1.44
1.6
1.76
Orderable Option TPS35xxxxL
9
10
11
Orderable Option TPS35xxxxM
45
50
55
Orderable Option TPS35xxxxN
90
100
110
tGI_VIT–
Glitch immunity VIT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
15
µs
tGI_VIT–
GI_VIT– Glitch immunity VIT–
IT–
5% VIT– overdrive#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER2
IT–#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER215µs
t
MR_PW
MR pin pulse duration to assert reset
100
ns
t
MR_PW
MR_PWMR
MR pin pulse duration to assert resetMR100ns
tP-WD
WDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
500
ns
tP-WD
P-WDWDI pulse duration to start next frame #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDVVDD > VIT–
DDIT–500ns
tHD-WDEN
WD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
200
µs
tHD-WDEN
HD-WDENWD-EN hold time to enable or disable WD operation #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDVVDD > VIT–
DDIT–200µs
tHD-SETx
SETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
VDD > VIT–
150
µs
tHD-SETx
HD-SETxSETx hold time to change WD timer setting #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDV
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244052/SFXKDP01NFDVVDD > VIT–
DDIT–150µs
tWD
Watchdog timeout period
Orderable Option TPS35xxxxB
0.8
1
1.2
ms
tWD
WDWatchdog timeout periodOrderable Option TPS35xxxxB0.811.2ms
Orderable Option TPS35xxxxC
4
5
6
Orderable Option TPS35xxxxC456
Orderable Option TPS35xxxxD
9
10
11
Orderable Option TPS35xxxxD91011
Orderable Option TPS35xxxxE
18
20
22
Orderable Option TPS35xxxxE182022
Orderable Option TPS35xxxxF
45
50
55
Orderable Option TPS35xxxxF455055
Orderable Option TPS35xxxxG
90
100
110
Orderable Option TPS35xxxxG90100110
Orderable Option TPS35xxxxH
180
200
220
Orderable Option TPS35xxxxH180200220
Orderable Option TPS35xxxxI
0.9
1
1.1
s
Orderable Option TPS35xxxxI0.911.1s
Orderable Option TPS35xxxxJ
1.26
1.4
1.54
Orderable Option TPS35xxxxJ1.261.41.54
Orderable Option TPS35xxxxK
1.44
1.6
1.76
Orderable Option TPS35xxxxK1.441.61.76
Orderable Option TPS35xxxxL
9
10
11
Orderable Option TPS35xxxxL91011
Orderable Option TPS35xxxxM
45
50
55
Orderable Option TPS35xxxxM455055
Orderable Option TPS35xxxxN
90
100
110
Orderable Option TPS35xxxxN90100110
Overdrive % = [(VDD/ VIT–) – 1] × 100%
Not production tested
Overdrive % = [(VDD/ VIT–) – 1] × 100%DDIT–Not production tested
Switching Characteristics
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTRT
Startup delay(4)
500
µs
tP_HL
RESET detect delay for VDD falling below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
30
50
µs
tSD
Watchdog startup delay
Orderable part number TPS35xA, TPS35xG
0
ms
Orderable part number TPS35xB, TPS35xH
180
200
220
Orderable part number TPS35xC, TPS35xI
450
500
550
Orderable part number TPS35xD, TPS35xJ
0.9
1
1.1
s
Orderable part number TPS35xE, TPS35xK
4.5
5
5.5
Orderable part number TPS35xF, TPS35xL
9
10
11
tD
Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
Orderable part number TPS35xxxxxxB
1.6
2
2.4
ms
Orderable part number TPS35xxxxxxC
9
10
11
ms
Orderable part number TPS35xxxxxxD
22.5
25
27.5
ms
Orderable part number TPS35xxxxxxE
45
50
55
ms
Orderable part number TPS35xxxxxxF
90
100
110
ms
Orderable part number TPS35xxxxxxG
180
200
220
ms
Orderable part number TPS35xxxxxxH
0.9
1
1.1
s
Orderable part number TPS35xxxxxxI
9
10
11
s
tWDO
Watchdog timeout delay
tD
s
t
MR_RES
Propagation delay from MR low to reset assertion
VDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
100
ns
t
MR_tD
Delay from MR release to reset deassert
VDD = 3.3 V,
MR = V
MR_L to V
MR_H
tD
s
tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay.
VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)
Switching Characteristics
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTRT
Startup delay(4)
500
µs
tP_HL
RESET detect delay for VDD falling below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
30
50
µs
tSD
Watchdog startup delay
Orderable part number TPS35xA, TPS35xG
0
ms
Orderable part number TPS35xB, TPS35xH
180
200
220
Orderable part number TPS35xC, TPS35xI
450
500
550
Orderable part number TPS35xD, TPS35xJ
0.9
1
1.1
s
Orderable part number TPS35xE, TPS35xK
4.5
5
5.5
Orderable part number TPS35xF, TPS35xL
9
10
11
tD
Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
Orderable part number TPS35xxxxxxB
1.6
2
2.4
ms
Orderable part number TPS35xxxxxxC
9
10
11
ms
Orderable part number TPS35xxxxxxD
22.5
25
27.5
ms
Orderable part number TPS35xxxxxxE
45
50
55
ms
Orderable part number TPS35xxxxxxF
90
100
110
ms
Orderable part number TPS35xxxxxxG
180
200
220
ms
Orderable part number TPS35xxxxxxH
0.9
1
1.1
s
Orderable part number TPS35xxxxxxI
9
10
11
s
tWDO
Watchdog timeout delay
tD
s
t
MR_RES
Propagation delay from MR low to reset assertion
VDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
100
ns
t
MR_tD
Delay from MR release to reset deassert
VDD = 3.3 V,
MR = V
MR_L to V
MR_H
tD
s
tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay.
VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTRT
Startup delay(4)
500
µs
tP_HL
RESET detect delay for VDD falling below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
30
50
µs
tSD
Watchdog startup delay
Orderable part number TPS35xA, TPS35xG
0
ms
Orderable part number TPS35xB, TPS35xH
180
200
220
Orderable part number TPS35xC, TPS35xI
450
500
550
Orderable part number TPS35xD, TPS35xJ
0.9
1
1.1
s
Orderable part number TPS35xE, TPS35xK
4.5
5
5.5
Orderable part number TPS35xF, TPS35xL
9
10
11
tD
Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
Orderable part number TPS35xxxxxxB
1.6
2
2.4
ms
Orderable part number TPS35xxxxxxC
9
10
11
ms
Orderable part number TPS35xxxxxxD
22.5
25
27.5
ms
Orderable part number TPS35xxxxxxE
45
50
55
ms
Orderable part number TPS35xxxxxxF
90
100
110
ms
Orderable part number TPS35xxxxxxG
180
200
220
ms
Orderable part number TPS35xxxxxxH
0.9
1
1.1
s
Orderable part number TPS35xxxxxxI
9
10
11
s
tWDO
Watchdog timeout delay
tD
s
t
MR_RES
Propagation delay from MR low to reset assertion
VDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
100
ns
t
MR_tD
Delay from MR release to reset deassert
VDD = 3.3 V,
MR = V
MR_L to V
MR_H
tD
s
At 1.04 V ≤ VDD ≤ 6 V, MR = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, WDO pull-up resistor (Rpull-up) = 100 kΩ to VDD, output RESET / WDO load (CLOAD) = 10 pF and over operating free-air temperature range –40℃ to 125℃, unless otherwise noted. VDD ramp rate ≤ 1 V/µs. Typical values are at TA = 25℃DDMR RESETpull-upWDOpull-upLOADA
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tSTRT
Startup delay(4)
500
µs
tP_HL
RESET detect delay for VDD falling below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
30
50
µs
tSD
Watchdog startup delay
Orderable part number TPS35xA, TPS35xG
0
ms
Orderable part number TPS35xB, TPS35xH
180
200
220
Orderable part number TPS35xC, TPS35xI
450
500
550
Orderable part number TPS35xD, TPS35xJ
0.9
1
1.1
s
Orderable part number TPS35xE, TPS35xK
4.5
5
5.5
Orderable part number TPS35xF, TPS35xL
9
10
11
tD
Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
Orderable part number TPS35xxxxxxB
1.6
2
2.4
ms
Orderable part number TPS35xxxxxxC
9
10
11
ms
Orderable part number TPS35xxxxxxD
22.5
25
27.5
ms
Orderable part number TPS35xxxxxxE
45
50
55
ms
Orderable part number TPS35xxxxxxF
90
100
110
ms
Orderable part number TPS35xxxxxxG
180
200
220
ms
Orderable part number TPS35xxxxxxH
0.9
1
1.1
s
Orderable part number TPS35xxxxxxI
9
10
11
s
tWDO
Watchdog timeout delay
tD
s
t
MR_RES
Propagation delay from MR low to reset assertion
VDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
100
ns
t
MR_tD
Delay from MR release to reset deassert
VDD = 3.3 V,
MR = V
MR_L to V
MR_H
tD
s
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tSTRT
Startup delay(4)
500
µs
tP_HL
RESET detect delay for VDD falling below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
30
50
µs
tSD
Watchdog startup delay
Orderable part number TPS35xA, TPS35xG
0
ms
Orderable part number TPS35xB, TPS35xH
180
200
220
Orderable part number TPS35xC, TPS35xI
450
500
550
Orderable part number TPS35xD, TPS35xJ
0.9
1
1.1
s
Orderable part number TPS35xE, TPS35xK
4.5
5
5.5
Orderable part number TPS35xF, TPS35xL
9
10
11
tD
Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
Orderable part number TPS35xxxxxxB
1.6
2
2.4
ms
Orderable part number TPS35xxxxxxC
9
10
11
ms
Orderable part number TPS35xxxxxxD
22.5
25
27.5
ms
Orderable part number TPS35xxxxxxE
45
50
55
ms
Orderable part number TPS35xxxxxxF
90
100
110
ms
Orderable part number TPS35xxxxxxG
180
200
220
ms
Orderable part number TPS35xxxxxxH
0.9
1
1.1
s
Orderable part number TPS35xxxxxxI
9
10
11
s
tWDO
Watchdog timeout delay
tD
s
t
MR_RES
Propagation delay from MR low to reset assertion
VDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
100
ns
t
MR_tD
Delay from MR release to reset deassert
VDD = 3.3 V,
MR = V
MR_L to V
MR_H
tD
s
tSTRT
Startup delay(4)
500
µs
tSTRT
STRTStartup delay(4)
(4)
500µs
tP_HL
RESET detect delay for VDD falling below VIT–
VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
30
50
µs
tP_HL
P_HLRESET detect delay for VDD falling below VIT–
IT–VDD : (VIT+ + 10%) to (VIT– – 10%)#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF1
DD IT+ IT–#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER4_SF13050µs
tSD
Watchdog startup delay
Orderable part number TPS35xA, TPS35xG
0
ms
tSD
SDWatchdog startup delayOrderable part number TPS35xA, TPS35xG0ms
Orderable part number TPS35xB, TPS35xH
180
200
220
Orderable part number TPS35xB, TPS35xH180200220
Orderable part number TPS35xC, TPS35xI
450
500
550
Orderable part number TPS35xC, TPS35xI450500550
Orderable part number TPS35xD, TPS35xJ
0.9
1
1.1
s
Orderable part number TPS35xD, TPS35xJ0.911.1s
Orderable part number TPS35xE, TPS35xK
4.5
5
5.5
Orderable part number TPS35xE, TPS35xK4.555.5
Orderable part number TPS35xF, TPS35xL
9
10
11
Orderable part number TPS35xF, TPS35xL91011
tD
Reset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
Orderable part number TPS35xxxxxxB
1.6
2
2.4
ms
tD
DReset time delay #GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1
#GUID-XXXXXXXX-SF0T-XXXX-XXXX-000000244220/A_SUPERVISOR_VVCM_7_TIMINGREQ_FOOTER3_SF1Orderable part number TPS35xxxxxxB1.622.4ms
Orderable part number TPS35xxxxxxC
9
10
11
ms
Orderable part number TPS35xxxxxxC91011ms
Orderable part number TPS35xxxxxxD
22.5
25
27.5
ms
Orderable part number TPS35xxxxxxD22.52527.5ms
Orderable part number TPS35xxxxxxE
45
50
55
ms
Orderable part number TPS35xxxxxxE455055ms
Orderable part number TPS35xxxxxxF
90
100
110
ms
Orderable part number TPS35xxxxxxF90100110ms
Orderable part number TPS35xxxxxxG
180
200
220
ms
Orderable part number TPS35xxxxxxG180200220ms
Orderable part number TPS35xxxxxxH
0.9
1
1.1
s
Orderable part number TPS35xxxxxxH0.911.1s
Orderable part number TPS35xxxxxxI
9
10
11
s
Orderable part number TPS35xxxxxxI91011s
tWDO
Watchdog timeout delay
tD
s
tWDO
WDOWatchdog timeout delaytD
Ds
t
MR_RES
Propagation delay from MR low to reset assertion
VDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
100
ns
t
MR_RES
MR_RESMRPropagation delay from MR low to reset assertionMRVDD ≥ VIT– + 0.2 V,
MR = V
MR_H to V
MR_L
DDIT–MR
MR_H MR
MR_LMR100ns
t
MR_tD
Delay from MR release to reset deassert
VDD = 3.3 V,
MR = V
MR_L to V
MR_H
tD
s
t
MR_tD
MR_tDMRDelay from MR release to reset deassertMR VDD = 3.3 V,
MR = V
MR_L to V
MR_H
DDMR
MR_L MR
MR_H MRtD
Ds
tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
Specified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay.
VDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)
tP_HL measured from threshold trip point (VIT–) to RESET assert. VIT+ = VIT– + VHYS
P_HLIT–IT+IT–HYSSpecified by design parameter. When VDD starts from less than the specified minimum VDD and then exceeds VIT+, reset is deasserted after the startup delay (tSTRT) + tD delay.DDIT+STRTDVDD voltage transitions from (VIT– - 10%) to (VIT– + 10%)IT– IT–
Timing Diagrams
*
Added a footnote to for tINIT
no
Functional Timing Diagram
Timing Diagrams
*
Added a footnote to for tINIT
no
*
Added a footnote to for tINIT
no
*
Added a footnote to for tINIT
no
*Added a footnote to for tINIT
INITno
Functional Timing Diagram
Functional Timing Diagram
Functional Timing Diagram
Functional Timing Diagram
Typical Characteristics
all curves are taken at TA = 25°C
(unless otherwise noted)
VIT-
Accuracy vs Temperature
VIT-
Accuracy Histogram
VIT- Hysteresis Vs Temperature
Supply Glitch
Immunity vs Overdrive
Timer Accuracy vs
Temperature
Timer Accuracy Histogram
tWD vs Capacitance
tD vs Capacitance
RESET VOL vs I
sink, VDD = 1.5 V
WDO VOL vs I
sink, VDD = 1.5 V
RESET VOL vs I sink, VDD = 3.3 V
WDO VOL vs I sink, VDD = 3.3 V
RESET VOH vs I source, VDD = 2.0 V
WDO VOH vs I source, VDD = 2.0 V
RESET VOH vs I source, VDD = 6.0 V
WDO VOH vs I source, VDD = 6.0 V
Supply Current
vs Power-Supply Voltage
Typical Characteristics
all curves are taken at TA = 25°C
(unless otherwise noted)
VIT-
Accuracy vs Temperature
VIT-
Accuracy Histogram
VIT- Hysteresis Vs Temperature
Supply Glitch
Immunity vs Overdrive
Timer Accuracy vs
Temperature
Timer Accuracy Histogram
tWD vs Capacitance
tD vs Capacitance
RESET VOL vs I
sink, VDD = 1.5 V
WDO VOL vs I
sink, VDD = 1.5 V
RESET VOL vs I sink, VDD = 3.3 V
WDO VOL vs I sink, VDD = 3.3 V
RESET VOH vs I source, VDD = 2.0 V
WDO VOH vs I source, VDD = 2.0 V
RESET VOH vs I source, VDD = 6.0 V
WDO VOH vs I source, VDD = 6.0 V
Supply Current
vs Power-Supply Voltage
all curves are taken at TA = 25°C
(unless otherwise noted)
VIT-
Accuracy vs Temperature
VIT-
Accuracy Histogram
VIT- Hysteresis Vs Temperature
Supply Glitch
Immunity vs Overdrive
Timer Accuracy vs
Temperature
Timer Accuracy Histogram
tWD vs Capacitance
tD vs Capacitance
RESET VOL vs I
sink, VDD = 1.5 V
WDO VOL vs I
sink, VDD = 1.5 V
RESET VOL vs I sink, VDD = 3.3 V
WDO VOL vs I sink, VDD = 3.3 V
RESET VOH vs I source, VDD = 2.0 V
WDO VOH vs I source, VDD = 2.0 V
RESET VOH vs I source, VDD = 6.0 V
WDO VOH vs I source, VDD = 6.0 V
Supply Current
vs Power-Supply Voltage
all curves are taken at TA = 25°C
(unless otherwise noted)A
VIT-
Accuracy vs Temperature
VIT-
Accuracy Histogram
VIT- Hysteresis Vs Temperature
Supply Glitch
Immunity vs Overdrive
Timer Accuracy vs
Temperature
Timer Accuracy Histogram
tWD vs Capacitance
tD vs Capacitance
RESET VOL vs I
sink, VDD = 1.5 V
WDO VOL vs I
sink, VDD = 1.5 V
RESET VOL vs I sink, VDD = 3.3 V
WDO VOL vs I sink, VDD = 3.3 V
RESET VOH vs I source, VDD = 2.0 V
WDO VOH vs I source, VDD = 2.0 V
RESET VOH vs I source, VDD = 6.0 V
WDO VOH vs I source, VDD = 6.0 V
Supply Current
vs Power-Supply Voltage
VIT-
Accuracy vs Temperature
VIT-
Accuracy vs TemperatureIT-
VIT-
Accuracy Histogram
VIT-
Accuracy HistogramIT-
VIT- Hysteresis Vs Temperature
VIT- Hysteresis Vs TemperatureIT-
Supply Glitch
Immunity vs Overdrive
Supply Glitch
Immunity vs Overdrive
Timer Accuracy vs
Temperature
Timer Accuracy vs
Temperature
Timer Accuracy Histogram
Timer Accuracy Histogram
tWD vs Capacitance
tWD vs CapacitanceWD
tD vs Capacitance
tD vs CapacitanceD
RESET VOL vs I
sink, VDD = 1.5 V
RESET VOL vs I
sink, VDD = 1.5 VOLsinkDD
WDO VOL vs I
sink, VDD = 1.5 V
WDO VOL vs I
sink, VDD = 1.5 VOLsinkDD
RESET VOL vs I sink, VDD = 3.3 V
RESET VOL vs I sink, VDD = 3.3 VOLsinkDD
WDO VOL vs I sink, VDD = 3.3 V
WDO VOL vs I sink, VDD = 3.3 VOLsinkDD
RESET VOH vs I source, VDD = 2.0 V
RESET VOH vs I source, VDD = 2.0 VOHsourceDD
WDO VOH vs I source, VDD = 2.0 V
WDO VOH vs I source, VDD = 2.0 VOHsourceDD
RESET VOH vs I source, VDD = 6.0 V
RESET VOH vs I source, VDD = 6.0 VOHsourceDD
WDO VOH vs I source, VDD = 6.0 V
WDO VOH vs I source, VDD = 6.0 VOHsourceDD
Supply Current
vs Power-Supply Voltage
Supply Current
vs Power-Supply Voltage
Detailed Description
Overview
The TPS35-Q1 is a high-accuracy
under voltage supervisor with an integrated
timeout watchdog timer device. The device
family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are
available in 4 different
pinout configurations. Each pinout offers access to different features to meet the various
application requirements. The device family is rated for
-Q100 applications.
Functional Block Diagrams
Pinout Option A
Pinout Option B
Pinout Option C
Pinout Option D
Feature Description
Voltage Supervisor
The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer
for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open.
Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.
The supervisor offers wide range of fixed
monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The
device asserts the RESET output when the VDD signal falls below VIT-
threshold. The device offers hysteresis functionality for voltage supervision. This
ensures the supply has recovered above the monitoring threshold before the RESET
output is deasserted. The TPS35-Q1 typical voltage hysteresis
(VHYS) is 5%. Along with the voltage hysteresis, the device keeps the
RESET output asserted for time duration tD after the supply has risen
above VIT+. The RESET output assert duration changes from tD
to tSTRT + tD if the VDD signal is ramping from voltage <
VPOR. The tD time duration can be programmable using an
external capacitor or fixed time options offered by the device.
The typical timing behavior for a voltage
supervisor and the RESET output is showcased in . The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the
device voltage supervisor output is asserted, the watchdog functionality will be
disabled including WDO assert control. The device resumes watchdog related
functionality only after the supply is stable and the tD time duration
has elapsed.
Voltage Supervisor Timing Diagram
Timeout Watchdog Timer
The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.
The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.
TPS35-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer
for additional details.
The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period. Refer
section to arrive at the relevant tWD value needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout D. The RESET or WDO is asserted for time tD
. Refer
to arrive at the relevant tD
value needed for application.
shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.
Timeout Watchdog Timer Operation
tWD Timer
The tWD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.
The TPS35-Q1, when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. #GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTB highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.
tWD (sec) = 4.95 x 106 x CCWD (F)
The TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for tWD ≥ 10 msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the orderable part number. Refer
section to identify mapping of orderable part number to tWD value.
The TPS35-Q1 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.
Watchdog Enable Disable Operation
The TPS35-Q1 supports
watchdog enable or disable functionality. This functionality is critical for
different use cases as listed below.
Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error
interrupt.
Keep watchdog disabled until host boots up.
The TPS35-Q1 supports
watchdog enable or disable functionality through either WD-EN pin (pin configuration
C) or SET[1:0] = 0b'01 (pin
configuration B) logic combination. For a given pinout
only one of these two methods is available for the user to disable watchdog
operation.
For a pinout which offers a WD-EN pin,
the watchdog enable disable functionality is controlled by the logic state of WD-EN
pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable
the watchdog operation. The WD-EN pin can be toggled any time during the device
operation. The diagram
shows timing behavior with WD-EN pin control.
Watchdog Enable: WD-EN Pin
Control
SET[1:0] = 0b'01 combination can be
used to disable watchdog operation with a pinout which offers SET1 and SET0 pins,
but does not include WD-EN pin. The SET pin logic states can be changed at any time
during watchdog operation. Refer
section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a
capacitance connected between CWD and GND pin. A capacitance value higher than
recommended or connect to GND leads to watchdog functionality getting disabled.
Capacitance based disable operation overrides the other two options mentioned above.
Changing capacitance on the fly does not enable or disable watchdog operation. A
power supply recycle or device recovery after UV
fault, MR low event is needed
to detect change in capacitance.
Ongoing watchdog frame is terminated
when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled.
For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. When
enabled the device immediately enters tWD
frame and start watchdog
monitoring operation.
tSD Watchdog Start Up Delay
The TPS35-Q1 supports watchdog
startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin
but the WDO output is not asserted. This feature allows time for the host complete
boot process before watchdog monitoring can take over. The start up delay helps
avoid unexpected WDO or RESET assert events
during boot. The tSD time is predetermined based on the device part
number selected. Refer
section
for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec
start up delay options.
The tSD frame is complete when the time
duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during
tSD time. The device exits the tSD frame and enters
watchdog monitoring phase after valid WDI transition. Failure to provide valid
transition on WDI pin triggers the watchdog error by asserting the WDO output
pin. For devices with only RESET output, the
RESET pin is asserted.
The tSD frame is not initiated when the
watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in
section.
shows the
operation for tSD time frame.
tSD Frame
Behavior
SET Pin Behavior
The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are:
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. showcases an example of the tWD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec.
tWD Scaling with SET0 Pin Only (Pin
Configuration A)
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
For pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
Selected pinout option can offer WD-EN pin along
with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin
controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination
operates as SET[1:0] = 0b'00.
Make sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec.
to diagrams show the timing behavior with respect to SETx status changes.
Watchdog Behavior with SETx Pin Status
Watchdog Operation with 2 SET Pins
Watchdog Operation with 1 SET Pin
Manual RESET
The TPS35-Q1 supports
manual reset functionality using MR pin.
MR pin when driven with voltage lower than 0.3 x VDD,
asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The
MR pin can be left floating. The internal pull up makes
sure the output is not asserted due to MR pin trigger.
The output is deasserted after
MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more
details.
MR Pin
Response
RESET and WDO Output
The TPS35-Q1 device can offer RESET or RESET with independent WDO
output pin. The output configuration is dependent on the pinout variant selected.
For a pinout which has only RESET output, the RESET output is asserted when VDD
voltage is below the monitored threshold or MR pin voltage is
lower than threshold or watchdog timer error is detected. For a pinout which has
independent RESET and WDO output pins, the RESET output is asserted when VDD voltage
is below the monitored threshold or MR pin voltage is lower
than threshold. WDO output is asserted only when watchdog timer error is detected.
RESET error has higher priority than WDO error. If RESET is asserted when WDO is
asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin
is deasserted and startup delay frame is terminated.
The output will be asserted for tD
time when any relevant events
described above are detected. The time tD
can be programmed by
connecting a capacitor between CRST pin and GND or device will assert tD
for fixed time duration as
selected by orderable part number. Refer
section for all
available options.
describes the relationship between capacitor value and the time tD
. Ensure the capacitance meets
the recommended operating range. Capacitance outside the recommended range can lead
to incorrect operation of the device.
t
D
(sec) = 4.95 x
106 x CCRST (F)
TPS35-Q1 also offers
a unique option of latched output. An orderable with latched output will hold the
output in asserted state indefinitely until the device is power cycled or the error
condition is addressed. If the output is latched
due to voltage supervisor undervoltage detection, the output latch will be
released when VDD voltage rises above the VIT- + VHYS
level. If the output is latched
due to MR pin low voltage, the output latch will be released
when MR pin voltage rises above 0.7 x VDD level. If
the output is latched due to watchdog timer error, the output latch will be released
when a WDI negative edge is detected or the device is shutdown and powered up again.
shows
timing behavior of the device with latched output configuration.
Output Latch Timing Behavior
Device Functional Modes
#GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_TV3_FWV_HVB
summarizes the functional modes of the TPS35-Q1.
Device Functional
Modes
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VDD ≥ VIT+
Disabled
Ignored
High
High
Enabled
tpulse
1 < tWD(min)
High
High
Enabled
tpulse
1 > tWD(max)
Low
High
Where tpulse is the time between falling edges on
WDI.
Detailed Description
Overview
The TPS35-Q1 is a high-accuracy
under voltage supervisor with an integrated
timeout watchdog timer device. The device
family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are
available in 4 different
pinout configurations. Each pinout offers access to different features to meet the various
application requirements. The device family is rated for
-Q100 applications.
Overview
The TPS35-Q1 is a high-accuracy
under voltage supervisor with an integrated
timeout watchdog timer device. The device
family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are
available in 4 different
pinout configurations. Each pinout offers access to different features to meet the various
application requirements. The device family is rated for
-Q100 applications.
The TPS35-Q1 is a high-accuracy
under voltage supervisor with an integrated
timeout watchdog timer device. The device
family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are
available in 4 different
pinout configurations. Each pinout offers access to different features to meet the various
application requirements. The device family is rated for
-Q100 applications.
The TPS35-Q1 is a high-accuracy
under voltage supervisor with an integrated
timeout watchdog timer device. The device
family supports multiple features related to watchdog operation in a compact 8 pin SOT23 package. The devices are
available in 4 different
pinout configurations. Each pinout offers access to different features to meet the various
application requirements. The device family is rated for
-Q100 applications.
TPS35-Q1under voltage supervisor with an integrated timeout 4The device family is rated for
-Q100 applications.
Functional Block Diagrams
Pinout Option A
Pinout Option B
Pinout Option C
Pinout Option D
Functional Block Diagrams
Pinout Option A
Pinout Option B
Pinout Option C
Pinout Option D
Pinout Option A
Pinout Option B
Pinout Option C
Pinout Option D
Pinout Option A
Pinout Option A
Pinout Option B
Pinout Option B
Pinout Option C
Pinout Option C
Pinout Option D
Pinout Option D
Feature Description
Voltage Supervisor
The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer
for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open.
Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.
The supervisor offers wide range of fixed
monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The
device asserts the RESET output when the VDD signal falls below VIT-
threshold. The device offers hysteresis functionality for voltage supervision. This
ensures the supply has recovered above the monitoring threshold before the RESET
output is deasserted. The TPS35-Q1 typical voltage hysteresis
(VHYS) is 5%. Along with the voltage hysteresis, the device keeps the
RESET output asserted for time duration tD after the supply has risen
above VIT+. The RESET output assert duration changes from tD
to tSTRT + tD if the VDD signal is ramping from voltage <
VPOR. The tD time duration can be programmable using an
external capacitor or fixed time options offered by the device.
The typical timing behavior for a voltage
supervisor and the RESET output is showcased in . The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the
device voltage supervisor output is asserted, the watchdog functionality will be
disabled including WDO assert control. The device resumes watchdog related
functionality only after the supply is stable and the tD time duration
has elapsed.
Voltage Supervisor Timing Diagram
Timeout Watchdog Timer
The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.
The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.
TPS35-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer
for additional details.
The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period. Refer
section to arrive at the relevant tWD value needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout D. The RESET or WDO is asserted for time tD
. Refer
to arrive at the relevant tD
value needed for application.
shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.
Timeout Watchdog Timer Operation
tWD Timer
The tWD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.
The TPS35-Q1, when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. #GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTB highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.
tWD (sec) = 4.95 x 106 x CCWD (F)
The TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for tWD ≥ 10 msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the orderable part number. Refer
section to identify mapping of orderable part number to tWD value.
The TPS35-Q1 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.
Watchdog Enable Disable Operation
The TPS35-Q1 supports
watchdog enable or disable functionality. This functionality is critical for
different use cases as listed below.
Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error
interrupt.
Keep watchdog disabled until host boots up.
The TPS35-Q1 supports
watchdog enable or disable functionality through either WD-EN pin (pin configuration
C) or SET[1:0] = 0b'01 (pin
configuration B) logic combination. For a given pinout
only one of these two methods is available for the user to disable watchdog
operation.
For a pinout which offers a WD-EN pin,
the watchdog enable disable functionality is controlled by the logic state of WD-EN
pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable
the watchdog operation. The WD-EN pin can be toggled any time during the device
operation. The diagram
shows timing behavior with WD-EN pin control.
Watchdog Enable: WD-EN Pin
Control
SET[1:0] = 0b'01 combination can be
used to disable watchdog operation with a pinout which offers SET1 and SET0 pins,
but does not include WD-EN pin. The SET pin logic states can be changed at any time
during watchdog operation. Refer
section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a
capacitance connected between CWD and GND pin. A capacitance value higher than
recommended or connect to GND leads to watchdog functionality getting disabled.
Capacitance based disable operation overrides the other two options mentioned above.
Changing capacitance on the fly does not enable or disable watchdog operation. A
power supply recycle or device recovery after UV
fault, MR low event is needed
to detect change in capacitance.
Ongoing watchdog frame is terminated
when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled.
For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. When
enabled the device immediately enters tWD
frame and start watchdog
monitoring operation.
tSD Watchdog Start Up Delay
The TPS35-Q1 supports watchdog
startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin
but the WDO output is not asserted. This feature allows time for the host complete
boot process before watchdog monitoring can take over. The start up delay helps
avoid unexpected WDO or RESET assert events
during boot. The tSD time is predetermined based on the device part
number selected. Refer
section
for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec
start up delay options.
The tSD frame is complete when the time
duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during
tSD time. The device exits the tSD frame and enters
watchdog monitoring phase after valid WDI transition. Failure to provide valid
transition on WDI pin triggers the watchdog error by asserting the WDO output
pin. For devices with only RESET output, the
RESET pin is asserted.
The tSD frame is not initiated when the
watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in
section.
shows the
operation for tSD time frame.
tSD Frame
Behavior
SET Pin Behavior
The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are:
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. showcases an example of the tWD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec.
tWD Scaling with SET0 Pin Only (Pin
Configuration A)
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
For pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
Selected pinout option can offer WD-EN pin along
with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin
controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination
operates as SET[1:0] = 0b'00.
Make sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec.
to diagrams show the timing behavior with respect to SETx status changes.
Watchdog Behavior with SETx Pin Status
Watchdog Operation with 2 SET Pins
Watchdog Operation with 1 SET Pin
Manual RESET
The TPS35-Q1 supports
manual reset functionality using MR pin.
MR pin when driven with voltage lower than 0.3 x VDD,
asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The
MR pin can be left floating. The internal pull up makes
sure the output is not asserted due to MR pin trigger.
The output is deasserted after
MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more
details.
MR Pin
Response
RESET and WDO Output
The TPS35-Q1 device can offer RESET or RESET with independent WDO
output pin. The output configuration is dependent on the pinout variant selected.
For a pinout which has only RESET output, the RESET output is asserted when VDD
voltage is below the monitored threshold or MR pin voltage is
lower than threshold or watchdog timer error is detected. For a pinout which has
independent RESET and WDO output pins, the RESET output is asserted when VDD voltage
is below the monitored threshold or MR pin voltage is lower
than threshold. WDO output is asserted only when watchdog timer error is detected.
RESET error has higher priority than WDO error. If RESET is asserted when WDO is
asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin
is deasserted and startup delay frame is terminated.
The output will be asserted for tD
time when any relevant events
described above are detected. The time tD
can be programmed by
connecting a capacitor between CRST pin and GND or device will assert tD
for fixed time duration as
selected by orderable part number. Refer
section for all
available options.
describes the relationship between capacitor value and the time tD
. Ensure the capacitance meets
the recommended operating range. Capacitance outside the recommended range can lead
to incorrect operation of the device.
t
D
(sec) = 4.95 x
106 x CCRST (F)
TPS35-Q1 also offers
a unique option of latched output. An orderable with latched output will hold the
output in asserted state indefinitely until the device is power cycled or the error
condition is addressed. If the output is latched
due to voltage supervisor undervoltage detection, the output latch will be
released when VDD voltage rises above the VIT- + VHYS
level. If the output is latched
due to MR pin low voltage, the output latch will be released
when MR pin voltage rises above 0.7 x VDD level. If
the output is latched due to watchdog timer error, the output latch will be released
when a WDI negative edge is detected or the device is shutdown and powered up again.
shows
timing behavior of the device with latched output configuration.
Output Latch Timing Behavior
Feature Description
Voltage Supervisor
The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer
for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open.
Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.
The supervisor offers wide range of fixed
monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The
device asserts the RESET output when the VDD signal falls below VIT-
threshold. The device offers hysteresis functionality for voltage supervision. This
ensures the supply has recovered above the monitoring threshold before the RESET
output is deasserted. The TPS35-Q1 typical voltage hysteresis
(VHYS) is 5%. Along with the voltage hysteresis, the device keeps the
RESET output asserted for time duration tD after the supply has risen
above VIT+. The RESET output assert duration changes from tD
to tSTRT + tD if the VDD signal is ramping from voltage <
VPOR. The tD time duration can be programmable using an
external capacitor or fixed time options offered by the device.
The typical timing behavior for a voltage
supervisor and the RESET output is showcased in . The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the
device voltage supervisor output is asserted, the watchdog functionality will be
disabled including WDO assert control. The device resumes watchdog related
functionality only after the supply is stable and the tD time duration
has elapsed.
Voltage Supervisor Timing Diagram
Voltage Supervisor
The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer
for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open.
Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.
The supervisor offers wide range of fixed
monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The
device asserts the RESET output when the VDD signal falls below VIT-
threshold. The device offers hysteresis functionality for voltage supervision. This
ensures the supply has recovered above the monitoring threshold before the RESET
output is deasserted. The TPS35-Q1 typical voltage hysteresis
(VHYS) is 5%. Along with the voltage hysteresis, the device keeps the
RESET output asserted for time duration tD after the supply has risen
above VIT+. The RESET output assert duration changes from tD
to tSTRT + tD if the VDD signal is ramping from voltage <
VPOR. The tD time duration can be programmable using an
external capacitor or fixed time options offered by the device.
The typical timing behavior for a voltage
supervisor and the RESET output is showcased in . The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the
device voltage supervisor output is asserted, the watchdog functionality will be
disabled including WDO assert control. The device resumes watchdog related
functionality only after the supply is stable and the tD time duration
has elapsed.
Voltage Supervisor Timing Diagram
The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer
for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open.
Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.
The supervisor offers wide range of fixed
monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The
device asserts the RESET output when the VDD signal falls below VIT-
threshold. The device offers hysteresis functionality for voltage supervision. This
ensures the supply has recovered above the monitoring threshold before the RESET
output is deasserted. The TPS35-Q1 typical voltage hysteresis
(VHYS) is 5%. Along with the voltage hysteresis, the device keeps the
RESET output asserted for time duration tD after the supply has risen
above VIT+. The RESET output assert duration changes from tD
to tSTRT + tD if the VDD signal is ramping from voltage <
VPOR. The tD time duration can be programmable using an
external capacitor or fixed time options offered by the device.
The typical timing behavior for a voltage
supervisor and the RESET output is showcased in . The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the
device voltage supervisor output is asserted, the watchdog functionality will be
disabled including WDO assert control. The device resumes watchdog related
functionality only after the supply is stable and the tD time duration
has elapsed.
Voltage Supervisor Timing Diagram
The TPS35-Q1 offers high accuracy under voltage supervisor function at very low quiescent current. The voltage supervisor function is always active. After the device powers up from VDD < VPOR, the RESET and WDO outputs will be actively driven when VDD is greater than VPOR. The device starts monitoring the supply level when the VDD voltage is greater than 1.04 V. The device will hold the RESET pin asserted for tSTRT + tD time after the VDD > VIT+ (VIT- + VHYS). Refer
for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open. TPS35-Q1PORPORSTRTDIT+IT-HYS
DDSTRTDevice pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.The supervisor offers wide range of fixed
monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The
device asserts the RESET output when the VDD signal falls below VIT-
threshold. The device offers hysteresis functionality for voltage supervision. This
ensures the supply has recovered above the monitoring threshold before the RESET
output is deasserted. The TPS35-Q1 typical voltage hysteresis
(VHYS) is 5%. Along with the voltage hysteresis, the device keeps the
RESET output asserted for time duration tD after the supply has risen
above VIT+. The RESET output assert duration changes from tD
to tSTRT + tD if the VDD signal is ramping from voltage <
VPOR. The tD time duration can be programmable using an
external capacitor or fixed time options offered by the device.IT-IT-TPS35-Q1HYSDIT+DSTRTDPORDThe typical timing behavior for a voltage
supervisor and the RESET output is showcased in . The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the
device voltage supervisor output is asserted, the watchdog functionality will be
disabled including WDO assert control. The device resumes watchdog related
functionality only after the supply is stable and the tD time duration
has elapsed.D
Voltage Supervisor Timing Diagram
Voltage Supervisor Timing Diagram
Timeout Watchdog Timer
The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.
The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.
TPS35-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer
for additional details.
The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period. Refer
section to arrive at the relevant tWD value needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout D. The RESET or WDO is asserted for time tD
. Refer
to arrive at the relevant tD
value needed for application.
shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.
Timeout Watchdog Timer Operation
tWD Timer
The tWD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.
The TPS35-Q1, when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. #GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTB highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.
tWD (sec) = 4.95 x 106 x CCWD (F)
The TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for tWD ≥ 10 msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the orderable part number. Refer
section to identify mapping of orderable part number to tWD value.
The TPS35-Q1 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.
Watchdog Enable Disable Operation
The TPS35-Q1 supports
watchdog enable or disable functionality. This functionality is critical for
different use cases as listed below.
Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error
interrupt.
Keep watchdog disabled until host boots up.
The TPS35-Q1 supports
watchdog enable or disable functionality through either WD-EN pin (pin configuration
C) or SET[1:0] = 0b'01 (pin
configuration B) logic combination. For a given pinout
only one of these two methods is available for the user to disable watchdog
operation.
For a pinout which offers a WD-EN pin,
the watchdog enable disable functionality is controlled by the logic state of WD-EN
pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable
the watchdog operation. The WD-EN pin can be toggled any time during the device
operation. The diagram
shows timing behavior with WD-EN pin control.
Watchdog Enable: WD-EN Pin
Control
SET[1:0] = 0b'01 combination can be
used to disable watchdog operation with a pinout which offers SET1 and SET0 pins,
but does not include WD-EN pin. The SET pin logic states can be changed at any time
during watchdog operation. Refer
section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a
capacitance connected between CWD and GND pin. A capacitance value higher than
recommended or connect to GND leads to watchdog functionality getting disabled.
Capacitance based disable operation overrides the other two options mentioned above.
Changing capacitance on the fly does not enable or disable watchdog operation. A
power supply recycle or device recovery after UV
fault, MR low event is needed
to detect change in capacitance.
Ongoing watchdog frame is terminated
when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled.
For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. When
enabled the device immediately enters tWD
frame and start watchdog
monitoring operation.
tSD Watchdog Start Up Delay
The TPS35-Q1 supports watchdog
startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin
but the WDO output is not asserted. This feature allows time for the host complete
boot process before watchdog monitoring can take over. The start up delay helps
avoid unexpected WDO or RESET assert events
during boot. The tSD time is predetermined based on the device part
number selected. Refer
section
for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec
start up delay options.
The tSD frame is complete when the time
duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during
tSD time. The device exits the tSD frame and enters
watchdog monitoring phase after valid WDI transition. Failure to provide valid
transition on WDI pin triggers the watchdog error by asserting the WDO output
pin. For devices with only RESET output, the
RESET pin is asserted.
The tSD frame is not initiated when the
watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in
section.
shows the
operation for tSD time frame.
tSD Frame
Behavior
SET Pin Behavior
The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are:
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. showcases an example of the tWD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec.
tWD Scaling with SET0 Pin Only (Pin
Configuration A)
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
For pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
Selected pinout option can offer WD-EN pin along
with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin
controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination
operates as SET[1:0] = 0b'00.
Make sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec.
to diagrams show the timing behavior with respect to SETx status changes.
Watchdog Behavior with SETx Pin Status
Watchdog Operation with 2 SET Pins
Watchdog Operation with 1 SET Pin
Timeout Watchdog Timer
The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.
The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.
TPS35-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer
for additional details.
The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period. Refer
section to arrive at the relevant tWD value needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout D. The RESET or WDO is asserted for time tD
. Refer
to arrive at the relevant tD
value needed for application.
shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.
Timeout Watchdog Timer Operation
The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.
The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.
TPS35-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer
for additional details.
The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period. Refer
section to arrive at the relevant tWD value needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout D. The RESET or WDO is asserted for time tD
. Refer
to arrive at the relevant tD
value needed for application.
shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.
Timeout Watchdog Timer Operation
The TPS35-Q1 offers high precision timeout watchdog timer monitoring. The device is available in multiple pinout options A to D which support multiple features to meet ever expanding needs of various applications. Ensure a correct pinout is selected to meet the application needs.TPS35-Q1D
The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.
TPS35-Q1 family offers various startup time delay options to ensure enough time is available for the host to complete boot operation. Please refer
for additional details.The timeout watchdog is active when the VDD voltage is higher than the VIT- + VHYS and the RESET is deasserted after the tD time. The watchdog stays active as long as VDD > VIT- and watchdog is enabled.IT-HYSDIT-TPS35-Q1
The timeout watchdog timer monitors the WDI pin for falling edge in the time frame defined by tWD time period. Refer
section to arrive at the relevant tWD value needed for application. The timer value is reset when a valid falling edge is detected on WDI pin in the tWD time duration. When a valid WDI transition is not detected in tWD time, the device asserts RESET output for pinout options A, B and C or WDO output for pinout D. The RESET or WDO is asserted for time tD
. Refer
to arrive at the relevant tD
value needed for application.WD
WDWDWDthe device asserts RESET output for pinout options A, B and C or WDO output for pinout DRESET or tD
D
tD
D
shows the basic operation for timeout watchdog timer operation. The TPS35-Q1 watchdog functionality supports multiple features. Details are available in following sub sections.TPS35-Q1
Timeout Watchdog Timer Operation
Timeout Watchdog Timer Operation
tWD Timer
The tWD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.
The TPS35-Q1, when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. #GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTB highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.
tWD (sec) = 4.95 x 106 x CCWD (F)
The TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for tWD ≥ 10 msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the orderable part number. Refer
section to identify mapping of orderable part number to tWD value.
The TPS35-Q1 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.
tWD TimerWD
The tWD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.
The TPS35-Q1, when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. #GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTB highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.
tWD (sec) = 4.95 x 106 x CCWD (F)
The TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for tWD ≥ 10 msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the orderable part number. Refer
section to identify mapping of orderable part number to tWD value.
The TPS35-Q1 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.
The tWD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.
The TPS35-Q1, when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. #GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTB highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.
tWD (sec) = 4.95 x 106 x CCWD (F)
The TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for tWD ≥ 10 msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the orderable part number. Refer
section to identify mapping of orderable part number to tWD value.
The TPS35-Q1 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.
The tWD timer for TPS35-Q1 can be set using an external capacitor connected between CWD pin and GND pin. This feature is available with pinout options A or B. Applications which are space constrained or need timer values which meet offered timer options, can benefit when using pinout options C or D. The TPS35-Q1 offers multiple fixed timer options ranging from 1 msec up-to 100 sec.WDTPS35-Q1 or DTPS35-Q1The TPS35-Q1, when using capacitance based timer, senses the capacitance value during the power up or after a RESET event. The capacitor is charged and discharged with known internal current source for one cycle to sense the capacitance value. The sensed value is used to arrive at tWD timer for the watchdog operation. This unique implementation helps reduce the continuous charge and discharge current for the capacitor, thus reducing overall current consumption. Continuous charge and discharge of capacitance creates wider dead time (no watchdog monitor functionality) when capacitor is discharging. The dead time is higher for high value of capacitance. The unique implementation of TPS35-Q1 helps avoid the dead time as the capacitance is not continuously charging or discharging under normal operation. Ensure CCWD is < 200 x CCRST for accurate calibration of capacitance. #GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTB highlights the relationship between tWD in second and CWD capacitance in farad. The tWD timer is 20% accurate for an ideal capacitor. Accuracy of the capacitance will have additional impact on the tWD time. Ensure the capacitance meets the recommended operating range. Capacitance outside the recommended range can lead to incorrect operation of the device.TPS35-Q1 or after a RESET eventWDTPS35-Q1CWDCRST#GUID-126A0EA8-DA64-4C35-A2AC-DECE33E8FC5E/EQUATION-BLOCK_XV1_5Z1_YTBWDWDWD
tWD (sec) = 4.95 x 106 x CCWD (F)
tWD (sec) = 4.95 x 106 x CCWD (F)WD6CWDThe TPS35-Q1 also offers wide selection of high accuracy fixed timer options starting from 1 msec to 100 sec including various industry standard values. The TPS35-Q1 fixed time options are ±10% accurate for tWD ≥ 10 msec. For tWD < 10 msec, the accuracy is ±20%. tWD value relevant to application can be identified from the orderable part number. Refer
section to identify mapping of orderable part number to tWD value.TPS35-Q1TPS35-Q1WDWDWD
WDThe TPS35-Q1 offers flexibility to change the tWD value on the fly by controlling the logic levels on the SETx pins.
section explains the advantages offered by this feature and the device behavior with various SETx pin combinations.TPS35-Q1WD
Watchdog Enable Disable Operation
The TPS35-Q1 supports
watchdog enable or disable functionality. This functionality is critical for
different use cases as listed below.
Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error
interrupt.
Keep watchdog disabled until host boots up.
The TPS35-Q1 supports
watchdog enable or disable functionality through either WD-EN pin (pin configuration
C) or SET[1:0] = 0b'01 (pin
configuration B) logic combination. For a given pinout
only one of these two methods is available for the user to disable watchdog
operation.
For a pinout which offers a WD-EN pin,
the watchdog enable disable functionality is controlled by the logic state of WD-EN
pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable
the watchdog operation. The WD-EN pin can be toggled any time during the device
operation. The diagram
shows timing behavior with WD-EN pin control.
Watchdog Enable: WD-EN Pin
Control
SET[1:0] = 0b'01 combination can be
used to disable watchdog operation with a pinout which offers SET1 and SET0 pins,
but does not include WD-EN pin. The SET pin logic states can be changed at any time
during watchdog operation. Refer
section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a
capacitance connected between CWD and GND pin. A capacitance value higher than
recommended or connect to GND leads to watchdog functionality getting disabled.
Capacitance based disable operation overrides the other two options mentioned above.
Changing capacitance on the fly does not enable or disable watchdog operation. A
power supply recycle or device recovery after UV
fault, MR low event is needed
to detect change in capacitance.
Ongoing watchdog frame is terminated
when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled.
For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. When
enabled the device immediately enters tWD
frame and start watchdog
monitoring operation.
Watchdog Enable Disable Operation
The TPS35-Q1 supports
watchdog enable or disable functionality. This functionality is critical for
different use cases as listed below.
Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error
interrupt.
Keep watchdog disabled until host boots up.
The TPS35-Q1 supports
watchdog enable or disable functionality through either WD-EN pin (pin configuration
C) or SET[1:0] = 0b'01 (pin
configuration B) logic combination. For a given pinout
only one of these two methods is available for the user to disable watchdog
operation.
For a pinout which offers a WD-EN pin,
the watchdog enable disable functionality is controlled by the logic state of WD-EN
pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable
the watchdog operation. The WD-EN pin can be toggled any time during the device
operation. The diagram
shows timing behavior with WD-EN pin control.
Watchdog Enable: WD-EN Pin
Control
SET[1:0] = 0b'01 combination can be
used to disable watchdog operation with a pinout which offers SET1 and SET0 pins,
but does not include WD-EN pin. The SET pin logic states can be changed at any time
during watchdog operation. Refer
section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a
capacitance connected between CWD and GND pin. A capacitance value higher than
recommended or connect to GND leads to watchdog functionality getting disabled.
Capacitance based disable operation overrides the other two options mentioned above.
Changing capacitance on the fly does not enable or disable watchdog operation. A
power supply recycle or device recovery after UV
fault, MR low event is needed
to detect change in capacitance.
Ongoing watchdog frame is terminated
when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled.
For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. When
enabled the device immediately enters tWD
frame and start watchdog
monitoring operation.
The TPS35-Q1 supports
watchdog enable or disable functionality. This functionality is critical for
different use cases as listed below.
Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error
interrupt.
Keep watchdog disabled until host boots up.
The TPS35-Q1 supports
watchdog enable or disable functionality through either WD-EN pin (pin configuration
C) or SET[1:0] = 0b'01 (pin
configuration B) logic combination. For a given pinout
only one of these two methods is available for the user to disable watchdog
operation.
For a pinout which offers a WD-EN pin,
the watchdog enable disable functionality is controlled by the logic state of WD-EN
pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable
the watchdog operation. The WD-EN pin can be toggled any time during the device
operation. The diagram
shows timing behavior with WD-EN pin control.
Watchdog Enable: WD-EN Pin
Control
SET[1:0] = 0b'01 combination can be
used to disable watchdog operation with a pinout which offers SET1 and SET0 pins,
but does not include WD-EN pin. The SET pin logic states can be changed at any time
during watchdog operation. Refer
section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a
capacitance connected between CWD and GND pin. A capacitance value higher than
recommended or connect to GND leads to watchdog functionality getting disabled.
Capacitance based disable operation overrides the other two options mentioned above.
Changing capacitance on the fly does not enable or disable watchdog operation. A
power supply recycle or device recovery after UV
fault, MR low event is needed
to detect change in capacitance.
Ongoing watchdog frame is terminated
when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled.
For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. When
enabled the device immediately enters tWD
frame and start watchdog
monitoring operation.
The TPS35-Q1 supports
watchdog enable or disable functionality. This functionality is critical for
different use cases as listed below.TPS35-Q1
Disable watchdog during firmware update to avoid host RESET.
Disable watchdog during software step-by-step debug operation.
Disable watchdog when performing critical task to avoid watchdog error
interrupt.
Keep watchdog disabled until host boots up.
Disable watchdog during firmware update to avoid host RESET.Disable watchdog during software step-by-step debug operation.Disable watchdog when performing critical task to avoid watchdog error
interrupt.Keep watchdog disabled until host boots up.The TPS35-Q1 supports
watchdog enable or disable functionality through either WD-EN pin (pin configuration
C) or SET[1:0] = 0b'01 (pin
configuration B) logic combination. For a given pinout
only one of these two methods is available for the user to disable watchdog
operation.TPS35-Q1For a pinout which offers a WD-EN pin,
the watchdog enable disable functionality is controlled by the logic state of WD-EN
pin. Drive WD-EN = 1 to enable the watchdog operation or drive WD-EN = 0 to disable
the watchdog operation. The WD-EN pin can be toggled any time during the device
operation. The diagram
shows timing behavior with WD-EN pin control.
Watchdog Enable: WD-EN Pin
Control
Watchdog Enable: WD-EN Pin
ControlSET[1:0] = 0b'01 combination can be
used to disable watchdog operation with a pinout which offers SET1 and SET0 pins,
but does not include WD-EN pin. The SET pin logic states can be changed at any time
during watchdog operation. Refer
section for additional details regarding SET[1:0] pin behavior.
Pinout options A, B offer watchdog timer control using a
capacitance connected between CWD and GND pin. A capacitance value higher than
recommended or connect to GND leads to watchdog functionality getting disabled.
Capacitance based disable operation overrides the other two options mentioned above.
Changing capacitance on the fly does not enable or disable watchdog operation. A
power supply recycle or device recovery after UV
fault, MR low event is needed
to detect change in capacitance. or device recovery after UV
fault, MR low eventMROngoing watchdog frame is terminated
when watchdog is disabled. WDO stays deasserted when watchdog operation is disabled.
For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. When
enabled the device immediately enters tWD
frame and start watchdog
monitoring operation.For a pinout with only RESET output, the RESET
can assert if supply supervisor error occurs. tWD
WD
tSD Watchdog Start Up Delay
The TPS35-Q1 supports watchdog
startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin
but the WDO output is not asserted. This feature allows time for the host complete
boot process before watchdog monitoring can take over. The start up delay helps
avoid unexpected WDO or RESET assert events
during boot. The tSD time is predetermined based on the device part
number selected. Refer
section
for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec
start up delay options.
The tSD frame is complete when the time
duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during
tSD time. The device exits the tSD frame and enters
watchdog monitoring phase after valid WDI transition. Failure to provide valid
transition on WDI pin triggers the watchdog error by asserting the WDO output
pin. For devices with only RESET output, the
RESET pin is asserted.
The tSD frame is not initiated when the
watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in
section.
shows the
operation for tSD time frame.
tSD Frame
Behavior
tSD Watchdog Start Up DelaySD
The TPS35-Q1 supports watchdog
startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin
but the WDO output is not asserted. This feature allows time for the host complete
boot process before watchdog monitoring can take over. The start up delay helps
avoid unexpected WDO or RESET assert events
during boot. The tSD time is predetermined based on the device part
number selected. Refer
section
for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec
start up delay options.
The tSD frame is complete when the time
duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during
tSD time. The device exits the tSD frame and enters
watchdog monitoring phase after valid WDI transition. Failure to provide valid
transition on WDI pin triggers the watchdog error by asserting the WDO output
pin. For devices with only RESET output, the
RESET pin is asserted.
The tSD frame is not initiated when the
watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in
section.
shows the
operation for tSD time frame.
tSD Frame
Behavior
The TPS35-Q1 supports watchdog
startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin
but the WDO output is not asserted. This feature allows time for the host complete
boot process before watchdog monitoring can take over. The start up delay helps
avoid unexpected WDO or RESET assert events
during boot. The tSD time is predetermined based on the device part
number selected. Refer
section
for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec
start up delay options.
The tSD frame is complete when the time
duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during
tSD time. The device exits the tSD frame and enters
watchdog monitoring phase after valid WDI transition. Failure to provide valid
transition on WDI pin triggers the watchdog error by asserting the WDO output
pin. For devices with only RESET output, the
RESET pin is asserted.
The tSD frame is not initiated when the
watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in
section.
shows the
operation for tSD time frame.
tSD Frame
Behavior
The TPS35-Q1 supports watchdog
startup delay feature. This feature is activated after power up or after a RESET assert event or after WDO
assert event. When tSD frame is active, the device monitors the WDI pin
but the WDO output is not asserted. This feature allows time for the host complete
boot process before watchdog monitoring can take over. The start up delay helps
avoid unexpected WDO or RESET assert events
during boot. The tSD time is predetermined based on the device part
number selected. Refer
section
for details to map the part number to tSD time. Pinout option A, B are available only in no delay or 10 sec
start up delay options.TPS35-Q1or after a RESET assert event SD or RESETSD
SDThe tSD frame is complete when the time
duration selected for tSD is over or host provides a valid transition on
the WDI pin. The host must provide a valid transition on the WDI pin during
tSD time. The device exits the tSD frame and enters
watchdog monitoring phase after valid WDI transition. Failure to provide valid
transition on WDI pin triggers the watchdog error by asserting the WDO output
pin. For devices with only RESET output, the
RESET pin is asserted.
SDSDSDSD For devices with only RESET output, the
RESET pin is asserted.The tSD frame is not initiated when the
watchdog functionality is enabled using WD-EN pin or SET[1:0] pin combination as described in
section.SD
shows the
operation for tSD time frame.SD
tSD Frame
Behavior
tSD Frame
BehaviorSD
SET Pin Behavior
The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are:
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. showcases an example of the tWD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec.
tWD Scaling with SET0 Pin Only (Pin
Configuration A)
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
For pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
Selected pinout option can offer WD-EN pin along
with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin
controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination
operates as SET[1:0] = 0b'00.
Make sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec.
to diagrams show the timing behavior with respect to SETx status changes.
Watchdog Behavior with SETx Pin Status
Watchdog Operation with 2 SET Pins
Watchdog Operation with 1 SET Pin
SET Pin Behavior
The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are:
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. showcases an example of the tWD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec.
tWD Scaling with SET0 Pin Only (Pin
Configuration A)
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
For pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
Selected pinout option can offer WD-EN pin along
with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin
controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination
operates as SET[1:0] = 0b'00.
Make sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec.
to diagrams show the timing behavior with respect to SETx status changes.
Watchdog Behavior with SETx Pin Status
Watchdog Operation with 2 SET Pins
Watchdog Operation with 1 SET Pin
The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are:
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD timer is over or terminated.
For a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. showcases an example of the tWD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec.
tWD Scaling with SET0 Pin Only (Pin
Configuration A)
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
For pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
Selected pinout option can offer WD-EN pin along
with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin
controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination
operates as SET[1:0] = 0b'00.
Make sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec.
to diagrams show the timing behavior with respect to SETx status changes.
Watchdog Behavior with SETx Pin Status
Watchdog Operation with 2 SET Pins
Watchdog Operation with 1 SET Pin
The TPS35-Q1 offers one or two SET pins based on the pinout option selected. SET pins offer flexibility to the user to program the tWD timer on the fly to meet various application requirements. Typical use cases where SET pin can be used are:
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
TPS35-Q1WD
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.
Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.
Use wide timeout timer when host is in sleep mode, change to small timeout operation when host is operational. Watchdog can be used to wake up the host after long duration to perform the application related activities before going back to sleep.Change to wide timeout timer when performing system critical tasks to make sure the watchdog does not interrupt the critical task. Change timer to application specified interval after the critical task is complete.The tWD timer value for the device is combination of timer selection based on the CWD pin or fixed timer value along with SET pin logic level. The base tWD timer value is decided based on the Watchdog Time selector in the
section. The SET pin logic level is decoded during the device power up. The SET pin value can be changed any time during the operation. SETx pin change which leads to change of watchdog timer value or enable disable state, terminates the ongoing watchdog frame immediately. SETx pins can be updated when WDO or RESET output is asserted as well. The updated tWD timer value will be applied after output is deasserted and the tSD timer is over or terminated.WDWD
or RESETWDSDFor a pinout which offers only SET0 pin to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. showcases an example of the tWD values for different SET0 logic levels when using Watchdog Time setting as option D = 10 msec.WD
WD
tWD Scaling with SET0 Pin Only (Pin
Configuration A)
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
tWD Scaling with SET0 Pin Only (Pin
Configuration A)WD
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
WATCHDOG TIME SCALING SELECTION
tWD
SET0 = 0
SET0 = 1
WATCHDOG TIME SCALING SELECTION
tWD
WATCHDOG TIME SCALING SELECTIONtWD
WD
SET0 = 0
SET0 = 1
SET0 = 0SET0 = 1
A
10 msec
20 msec
B
10 msec
40 msec
C
10 msec
80 msec
D
10 msec
160 msec
E
10 msec
320 msec
F
10 msec
640 msec
G
10 msec
1280 msec
A
10 msec
20 msec
A10 msec20 msec
B
10 msec
40 msec
B10 msec40 msec
C
10 msec
80 msec
C10 msec80 msec
D
10 msec
160 msec
D10 msec160 msec
E
10 msec
320 msec
E10 msec320 msec
F
10 msec
640 msec
F10 msec640 msec
G
10 msec
1280 msec
G10 msec1280 msecFor pinouts which offer both SET0 & SET1 pins to the user, the tWD multiplier value is decided based on the Watchdog Time Scaling selector in the
section. Two SETx pins offer 3 different time scaling options. The SET[1:0] = 0b'01 combination disables the watchdog operation. showcases an example of the tWD values for different SET[1:0] logic levels when using Watchdog Time setting as option G = 100 msec. The package pin out selected does not offer WD-EN pin.WD
WD
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
tWD Scaling with SET0 & SET1
Pins, WD-EN Pin Not Available (Pin Configuration B)WD
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
WATCHDOG TIME SCALING SELECTION
tWD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
WATCHDOG TIME SCALING SELECTION
tWD
WATCHDOG TIME SCALING SELECTIONtWD
WD
SET[1:0] = 0b'00
SET[1:0] = 0b'01
SET[1:0] = 0b'10
SET[1:0] = 0b'11
SET[1:0] = 0b'00SET[1:0] = 0b'01SET[1:0] = 0b'10SET[1:0] = 0b'11
A
100 msec
Watchdog disable
200 msec
400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
A
100 msec
Watchdog disable
200 msec
400 msec
A100 msecWatchdog disable200 msec400 msec
B
100 msec
Watchdog disable
400 msec
800 msec
B100 msecWatchdog disable400 msec800 msec
C
100 msec
Watchdog disable
800 msec
1600 msec
C100 msecWatchdog disable800 msec1600 msec
D
100 msec
Watchdog disable
1600 msec
3200 msec
D100 msecWatchdog disable1600 msec3200 msec
E
100 msec
Watchdog disable
3200 msec
6400 msec
E100 msecWatchdog disable3200 msec6400 msec
F
100 msec
Watchdog disable
6400 msec
12800 msec
F100 msecWatchdog disable6400 msec12800 msec
G
100 msec
Watchdog disable
12800 msec
25600 msec
G100 msecWatchdog disable12800 msec25600 msecSelected pinout option can offer WD-EN pin along
with SET[1:0] pins (Pin Configuration C, D). With this pinout, the WD-EN pin
controls watchdog enable and disable operation. The SET[1:0] = 0b'01 combination
operates as SET[1:0] = 0b'00. , DMake sure the tWD value with SETx multiplier does not exceed 640 sec. If a selection of timer and multiplier results in tWD > 640 sec, the timer value will be restricted to 640 sec.WDWD
to diagrams show the timing behavior with respect to SETx status changes.
Watchdog Behavior with SETx Pin Status
Watchdog Behavior with SETx Pin Status
Watchdog Operation with 2 SET Pins
Watchdog Operation with 2 SET Pins
Watchdog Operation with 1 SET Pin
Watchdog Operation with 1 SET Pin
Manual RESET
The TPS35-Q1 supports
manual reset functionality using MR pin.
MR pin when driven with voltage lower than 0.3 x VDD,
asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The
MR pin can be left floating. The internal pull up makes
sure the output is not asserted due to MR pin trigger.
The output is deasserted after
MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more
details.
MR Pin
Response
Manual RESET
The TPS35-Q1 supports
manual reset functionality using MR pin.
MR pin when driven with voltage lower than 0.3 x VDD,
asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The
MR pin can be left floating. The internal pull up makes
sure the output is not asserted due to MR pin trigger.
The output is deasserted after
MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more
details.
MR Pin
Response
The TPS35-Q1 supports
manual reset functionality using MR pin.
MR pin when driven with voltage lower than 0.3 x VDD,
asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The
MR pin can be left floating. The internal pull up makes
sure the output is not asserted due to MR pin trigger.
The output is deasserted after
MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more
details.
MR Pin
Response
The TPS35-Q1 supports
manual reset functionality using MR pin.
MR pin when driven with voltage lower than 0.3 x VDD,
asserts the RESET output. The MR pin has 100 kΩ pull up to VDD. The
MR pin can be left floating. The internal pull up makes
sure the output is not asserted due to MR pin trigger.TPS35-Q1MRMRRESETMRMRMRThe output is deasserted after
MR pin voltage rises above 0.7 x VDD voltage and time tD is elapsed. Refer for more
details.MR and time tD is elapsedD
MR Pin
Response
MR Pin
ResponseMR
RESET and WDO Output
The TPS35-Q1 device can offer RESET or RESET with independent WDO
output pin. The output configuration is dependent on the pinout variant selected.
For a pinout which has only RESET output, the RESET output is asserted when VDD
voltage is below the monitored threshold or MR pin voltage is
lower than threshold or watchdog timer error is detected. For a pinout which has
independent RESET and WDO output pins, the RESET output is asserted when VDD voltage
is below the monitored threshold or MR pin voltage is lower
than threshold. WDO output is asserted only when watchdog timer error is detected.
RESET error has higher priority than WDO error. If RESET is asserted when WDO is
asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin
is deasserted and startup delay frame is terminated.
The output will be asserted for tD
time when any relevant events
described above are detected. The time tD
can be programmed by
connecting a capacitor between CRST pin and GND or device will assert tD
for fixed time duration as
selected by orderable part number. Refer
section for all
available options.
describes the relationship between capacitor value and the time tD
. Ensure the capacitance meets
the recommended operating range. Capacitance outside the recommended range can lead
to incorrect operation of the device.
t
D
(sec) = 4.95 x
106 x CCRST (F)
TPS35-Q1 also offers
a unique option of latched output. An orderable with latched output will hold the
output in asserted state indefinitely until the device is power cycled or the error
condition is addressed. If the output is latched
due to voltage supervisor undervoltage detection, the output latch will be
released when VDD voltage rises above the VIT- + VHYS
level. If the output is latched
due to MR pin low voltage, the output latch will be released
when MR pin voltage rises above 0.7 x VDD level. If
the output is latched due to watchdog timer error, the output latch will be released
when a WDI negative edge is detected or the device is shutdown and powered up again.
shows
timing behavior of the device with latched output configuration.
Output Latch Timing Behavior
RESET and WDO OutputRESET and
The TPS35-Q1 device can offer RESET or RESET with independent WDO
output pin. The output configuration is dependent on the pinout variant selected.
For a pinout which has only RESET output, the RESET output is asserted when VDD
voltage is below the monitored threshold or MR pin voltage is
lower than threshold or watchdog timer error is detected. For a pinout which has
independent RESET and WDO output pins, the RESET output is asserted when VDD voltage
is below the monitored threshold or MR pin voltage is lower
than threshold. WDO output is asserted only when watchdog timer error is detected.
RESET error has higher priority than WDO error. If RESET is asserted when WDO is
asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin
is deasserted and startup delay frame is terminated.
The output will be asserted for tD
time when any relevant events
described above are detected. The time tD
can be programmed by
connecting a capacitor between CRST pin and GND or device will assert tD
for fixed time duration as
selected by orderable part number. Refer
section for all
available options.
describes the relationship between capacitor value and the time tD
. Ensure the capacitance meets
the recommended operating range. Capacitance outside the recommended range can lead
to incorrect operation of the device.
t
D
(sec) = 4.95 x
106 x CCRST (F)
TPS35-Q1 also offers
a unique option of latched output. An orderable with latched output will hold the
output in asserted state indefinitely until the device is power cycled or the error
condition is addressed. If the output is latched
due to voltage supervisor undervoltage detection, the output latch will be
released when VDD voltage rises above the VIT- + VHYS
level. If the output is latched
due to MR pin low voltage, the output latch will be released
when MR pin voltage rises above 0.7 x VDD level. If
the output is latched due to watchdog timer error, the output latch will be released
when a WDI negative edge is detected or the device is shutdown and powered up again.
shows
timing behavior of the device with latched output configuration.
Output Latch Timing Behavior
The TPS35-Q1 device can offer RESET or RESET with independent WDO
output pin. The output configuration is dependent on the pinout variant selected.
For a pinout which has only RESET output, the RESET output is asserted when VDD
voltage is below the monitored threshold or MR pin voltage is
lower than threshold or watchdog timer error is detected. For a pinout which has
independent RESET and WDO output pins, the RESET output is asserted when VDD voltage
is below the monitored threshold or MR pin voltage is lower
than threshold. WDO output is asserted only when watchdog timer error is detected.
RESET error has higher priority than WDO error. If RESET is asserted when WDO is
asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin
is deasserted and startup delay frame is terminated.
The output will be asserted for tD
time when any relevant events
described above are detected. The time tD
can be programmed by
connecting a capacitor between CRST pin and GND or device will assert tD
for fixed time duration as
selected by orderable part number. Refer
section for all
available options.
describes the relationship between capacitor value and the time tD
. Ensure the capacitance meets
the recommended operating range. Capacitance outside the recommended range can lead
to incorrect operation of the device.
t
D
(sec) = 4.95 x
106 x CCRST (F)
TPS35-Q1 also offers
a unique option of latched output. An orderable with latched output will hold the
output in asserted state indefinitely until the device is power cycled or the error
condition is addressed. If the output is latched
due to voltage supervisor undervoltage detection, the output latch will be
released when VDD voltage rises above the VIT- + VHYS
level. If the output is latched
due to MR pin low voltage, the output latch will be released
when MR pin voltage rises above 0.7 x VDD level. If
the output is latched due to watchdog timer error, the output latch will be released
when a WDI negative edge is detected or the device is shutdown and powered up again.
shows
timing behavior of the device with latched output configuration.
Output Latch Timing Behavior
The TPS35-Q1 device can offer RESET or RESET with independent WDO
output pin. The output configuration is dependent on the pinout variant selected.
For a pinout which has only RESET output, the RESET output is asserted when VDD
voltage is below the monitored threshold or MR pin voltage is
lower than threshold or watchdog timer error is detected. For a pinout which has
independent RESET and WDO output pins, the RESET output is asserted when VDD voltage
is below the monitored threshold or MR pin voltage is lower
than threshold. WDO output is asserted only when watchdog timer error is detected.
RESET error has higher priority than WDO error. If RESET is asserted when WDO is
asserted, the device deasserts the WDO pin and watchdog is disabled until RESET pin
is deasserted and startup delay frame is terminated.TPS35-Q1MRMRThe output will be asserted for tD
time when any relevant events
described above are detected. The time tD
can be programmed by
connecting a capacitor between CRST pin and GND or device will assert tD
for fixed time duration as
selected by orderable part number. Refer
section for all
available options.tD
DtD
DtD
D
describes the relationship between capacitor value and the time tD
. Ensure the capacitance meets
the recommended operating range. Capacitance outside the recommended range can lead
to incorrect operation of the device.tD
D
t
D
(sec) = 4.95 x
106 x CCRST (F)
t
D
(sec) = 4.95 x
106 x CCRST (F)
D
D6CRST
TPS35-Q1 also offers
a unique option of latched output. An orderable with latched output will hold the
output in asserted state indefinitely until the device is power cycled or the error
condition is addressed. If the output is latched
due to voltage supervisor undervoltage detection, the output latch will be
released when VDD voltage rises above the VIT- + VHYS
level. If the output is latched
due to MR pin low voltage, the output latch will be released
when MR pin voltage rises above 0.7 x VDD level. If
the output is latched due to watchdog timer error, the output latch will be released
when a WDI negative edge is detected or the device is shutdown and powered up again.
shows
timing behavior of the device with latched output configuration.TPS35-Q1If the output is latched
due to voltage supervisor undervoltage detection, the output latch will be
released when VDD voltage rises above the VIT- + VHYS
level. IT-HYSMRMRDD
Output Latch Timing Behavior
Output Latch Timing Behavior
Device Functional Modes
#GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_TV3_FWV_HVB
summarizes the functional modes of the TPS35-Q1.
Device Functional
Modes
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VDD ≥ VIT+
Disabled
Ignored
High
High
Enabled
tpulse
1 < tWD(min)
High
High
Enabled
tpulse
1 > tWD(max)
Low
High
Where tpulse is the time between falling edges on
WDI.
Device Functional Modes
#GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_TV3_FWV_HVB
summarizes the functional modes of the TPS35-Q1.
Device Functional
Modes
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VDD ≥ VIT+
Disabled
Ignored
High
High
Enabled
tpulse
1 < tWD(min)
High
High
Enabled
tpulse
1 > tWD(max)
Low
High
Where tpulse is the time between falling edges on
WDI.
#GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_TV3_FWV_HVB
summarizes the functional modes of the TPS35-Q1.
Device Functional
Modes
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VDD ≥ VIT+
Disabled
Ignored
High
High
Enabled
tpulse
1 < tWD(min)
High
High
Enabled
tpulse
1 > tWD(max)
Low
High
Where tpulse is the time between falling edges on
WDI.
#GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_TV3_FWV_HVB
summarizes the functional modes of the TPS35-Q1.
#GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_TV3_FWV_HVB
#GUID-B008A25A-278A-4B38-AFBB-A738DE66DE26/TABLE_TV3_FWV_HVBTPS35-Q1
Device Functional
Modes
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VDD ≥ VIT+
Disabled
Ignored
High
High
Enabled
tpulse
1 < tWD(min)
High
High
Enabled
tpulse
1 > tWD(max)
Low
High
Device Functional
Modes
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VDD ≥ VIT+
Disabled
Ignored
High
High
Enabled
tpulse
1 < tWD(min)
High
High
Enabled
tpulse
1 > tWD(max)
Low
High
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDD
WATCHDOG STATUS
WDI
WDO
RESET
VDDWATCHDOG STATUSWDI
WDO
WDO
RESET
RESET
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VDD ≥ VIT+
Disabled
Ignored
High
High
Enabled
tpulse
1 < tWD(min)
High
High
Enabled
tpulse
1 > tWD(max)
Low
High
VDD <
VPOR
Not Applicable
—
Undefined
Undefined
VDD <
VPOR
DDPORNot Applicable—UndefinedUndefined
VPOR ≤
VDD < VIT-
Not Applicable
Ignored
High
Low
VPOR ≤
VDD < VIT-
PORDDIT-Not ApplicableIgnoredHighLow
VDD ≥ VIT+
Disabled
Ignored
High
High
VDD ≥ VIT+
DDIT+DisabledIgnoredHighHigh
Enabled
tpulse
1 < tWD(min)
High
High
Enabledtpulse
1 < tWD(min)
pulse1WD(min)HighHigh
Enabled
tpulse
1 > tWD(max)
Low
High
Enabledtpulse
1 > tWD(max)
pulse1WD(max)LowHigh
Where tpulse is the time between falling edges on
WDI.
Where tpulse is the time between falling edges on
WDI.pulse
Application and Implementation
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Application Information
The following sections describe in detail proper device implementation, depending on the final application requirements.
CRST Delay
The TPS35-Q1 features two options
for setting the reset delay
(tD): using a fixed timing and programming the timing through
an external capacitor.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Adjustable Capacitor Timing
The TPS35-Q1 also offers
programmable reset delay option when using pinout A and B. The TPS35-Q1 can be programmed to have a desired reset delay by
connecting a capacitor between CRST pin and GND. The typical delay time resulting
from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is
the capacitance in farads.
tD (sec) = 4.95 ×
106 × CCRST (F)
To minimize the difference between the calculated
reset delay time and the actual reset delay time, use a use a high-quality ceramic
dielectric COG capacitor and minimize parasitic board capacitance around this pin.
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026
lists the reset delay time ideal capacitor values for CCRST.
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
Minimum and maximum values are calculated using ideal capacitors.
Watchdog Timer Functionality
The TPS35-Q1 features two options
for setting the watchdog timer (tWD
): using a fixed timing and
programming the timing through an external capacitor.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Adjustable Capacitor Timings
Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.
Typical Applications
Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
The TPS35-Q1 features high-accuracy (1.2% maximum)
voltage supervising along with on-the-fly adjustable watchdog timing in order to
monitor critical processing elements in systems.
Microcontroller Supply and
Watchdog Monitoring Circuit
Design Requirements
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Detailed Design Procedure
Setting the Voltage Threshold
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.
Meeting the Watchdog Timeout Period
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.
Setting the Reset Delay
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.
Setting the Startup Delay and Output Topology
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.
Calculating the RESET Pullup Resistor
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.
Open-Drain RESET Configuration
Application and Implementation
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Information in the following applications sections is not part of the TI
component specification, and TI does not warrant its accuracy or completeness.
TI’s customers are responsible for determining suitability of components for
their purposes, as well as validating and testing their design implementation to
confirm system functionality.
Application Information
The following sections describe in detail proper device implementation, depending on the final application requirements.
CRST Delay
The TPS35-Q1 features two options
for setting the reset delay
(tD): using a fixed timing and programming the timing through
an external capacitor.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Adjustable Capacitor Timing
The TPS35-Q1 also offers
programmable reset delay option when using pinout A and B. The TPS35-Q1 can be programmed to have a desired reset delay by
connecting a capacitor between CRST pin and GND. The typical delay time resulting
from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is
the capacitance in farads.
tD (sec) = 4.95 ×
106 × CCRST (F)
To minimize the difference between the calculated
reset delay time and the actual reset delay time, use a use a high-quality ceramic
dielectric COG capacitor and minimize parasitic board capacitance around this pin.
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026
lists the reset delay time ideal capacitor values for CCRST.
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
Minimum and maximum values are calculated using ideal capacitors.
Watchdog Timer Functionality
The TPS35-Q1 features two options
for setting the watchdog timer (tWD
): using a fixed timing and
programming the timing through an external capacitor.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Adjustable Capacitor Timings
Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.
Application Information
The following sections describe in detail proper device implementation, depending on the final application requirements.
The following sections describe in detail proper device implementation, depending on the final application requirements.
The following sections describe in detail proper device implementation, depending on the final application requirements.
CRST Delay
The TPS35-Q1 features two options
for setting the reset delay
(tD): using a fixed timing and programming the timing through
an external capacitor.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Adjustable Capacitor Timing
The TPS35-Q1 also offers
programmable reset delay option when using pinout A and B. The TPS35-Q1 can be programmed to have a desired reset delay by
connecting a capacitor between CRST pin and GND. The typical delay time resulting
from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is
the capacitance in farads.
tD (sec) = 4.95 ×
106 × CCRST (F)
To minimize the difference between the calculated
reset delay time and the actual reset delay time, use a use a high-quality ceramic
dielectric COG capacitor and minimize parasitic board capacitance around this pin.
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026
lists the reset delay time ideal capacitor values for CCRST.
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
Minimum and maximum values are calculated using ideal capacitors.
CRST Delay
The TPS35-Q1 features two options
for setting the reset delay
(tD): using a fixed timing and programming the timing through
an external capacitor.
The TPS35-Q1 features two options
for setting the reset delay
(tD): using a fixed timing and programming the timing through
an external capacitor.
The TPS35-Q1 features two options
for setting the reset delay
(tD): using a fixed timing and programming the timing through
an external capacitor.TPS35-Q1 (tD)D
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.WD
Adjustable Capacitor Timing
The TPS35-Q1 also offers
programmable reset delay option when using pinout A and B. The TPS35-Q1 can be programmed to have a desired reset delay by
connecting a capacitor between CRST pin and GND. The typical delay time resulting
from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is
the capacitance in farads.
tD (sec) = 4.95 ×
106 × CCRST (F)
To minimize the difference between the calculated
reset delay time and the actual reset delay time, use a use a high-quality ceramic
dielectric COG capacitor and minimize parasitic board capacitance around this pin.
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026
lists the reset delay time ideal capacitor values for CCRST.
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
Minimum and maximum values are calculated using ideal capacitors.
Adjustable Capacitor Timing
The TPS35-Q1 also offers
programmable reset delay option when using pinout A and B. The TPS35-Q1 can be programmed to have a desired reset delay by
connecting a capacitor between CRST pin and GND. The typical delay time resulting
from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is
the capacitance in farads.
tD (sec) = 4.95 ×
106 × CCRST (F)
To minimize the difference between the calculated
reset delay time and the actual reset delay time, use a use a high-quality ceramic
dielectric COG capacitor and minimize parasitic board capacitance around this pin.
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026
lists the reset delay time ideal capacitor values for CCRST.
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
Minimum and maximum values are calculated using ideal capacitors.
The TPS35-Q1 also offers
programmable reset delay option when using pinout A and B. The TPS35-Q1 can be programmed to have a desired reset delay by
connecting a capacitor between CRST pin and GND. The typical delay time resulting
from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is
the capacitance in farads.
tD (sec) = 4.95 ×
106 × CCRST (F)
To minimize the difference between the calculated
reset delay time and the actual reset delay time, use a use a high-quality ceramic
dielectric COG capacitor and minimize parasitic board capacitance around this pin.
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026
lists the reset delay time ideal capacitor values for CCRST.
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
Minimum and maximum values are calculated using ideal capacitors.
The TPS35-Q1 also offers
programmable reset delay option when using pinout A and B. The TPS35-Q1 can be programmed to have a desired reset delay by
connecting a capacitor between CRST pin and GND. The typical delay time resulting
from a given external capacitance on the CRST pin can be calculated by #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12 , where tD is the reset delay time in seconds and CCRST is
the capacitance in farads.TPS35-Q1TPS35-Q1#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-12DCRSTtD (sec) = 4.95 ×
106 × CCRST (F)D6CRSTTo minimize the difference between the calculated
reset delay time and the actual reset delay time, use a use a high-quality ceramic
dielectric COG capacitor and minimize parasitic board capacitance around this pin.
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026
lists the reset delay time ideal capacitor values for CCRST.#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/SBVS3011026CRST
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
Reset Delay Time for Common Ideal Capacitor Values
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
CCRST
RESETDELAY TIME (tD)
UNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
CCRST
RESETDELAY TIME (tD)
UNIT
CCRST
CRST
RESETDELAY TIME (tD)RESETDUNIT
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
TYP
MAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
MIN #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39TYPMAX #GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
#GUID-7710661D-BC6A-40DC-BDC1-A7B294C2058B/T4523365-39
10 nF
39.6
49.5
59.4
ms
100 nF
396
495
594
ms
1 μF
3960
4950
5940
ms
10 nF
39.6
49.5
59.4
ms
10 nF39.649.559.4ms
100 nF
396
495
594
ms
100 nF396495594ms
1 μF
3960
4950
5940
ms
1 μF396049505940ms
Minimum and maximum values are calculated using ideal capacitors.
Minimum and maximum values are calculated using ideal capacitors.
Watchdog Timer Functionality
The TPS35-Q1 features two options
for setting the watchdog timer (tWD
): using a fixed timing and
programming the timing through an external capacitor.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Adjustable Capacitor Timings
Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.
Watchdog Timer FunctionalityTimer
The TPS35-Q1 features two options
for setting the watchdog timer (tWD
): using a fixed timing and
programming the timing through an external capacitor.
The TPS35-Q1 features two options
for setting the watchdog timer (tWD
): using a fixed timing and
programming the timing through an external capacitor.
The TPS35-Q1 features two options
for setting the watchdog timer (tWD
): using a fixed timing and
programming the timing through an external capacitor.TPS35-Q1tWD
WD
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Factory-Programmed watchdog Timing
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.
Fixed watchdog
timings are available using pinout C and D. Using these timings enables a
high-precision, 10% accurate watchdog timer tWD.WD
Adjustable Capacitor Timings
Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.
Adjustable Capacitor Timings
Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.
Adjustable tWD timing is achievable by connecting a capacitor to the CWD pin. If this method is used, please consult for calculating typical tWD values using ideal capacitors. Capacitor tolerances cause the actual device timing to vary such that the minimum of tWD can decrease and the maximum of tWD can increase by the capacitor tolerance. For the most accurate timing, use ceramic capacitors with COG dielectric material.WDWDWDWD
Typical Applications
Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
The TPS35-Q1 features high-accuracy (1.2% maximum)
voltage supervising along with on-the-fly adjustable watchdog timing in order to
monitor critical processing elements in systems.
Microcontroller Supply and
Watchdog Monitoring Circuit
Design Requirements
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Detailed Design Procedure
Setting the Voltage Threshold
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.
Meeting the Watchdog Timeout Period
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.
Setting the Reset Delay
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.
Setting the Startup Delay and Output Topology
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.
Calculating the RESET Pullup Resistor
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.
Open-Drain RESET Configuration
Typical Applications
Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
The TPS35-Q1 features high-accuracy (1.2% maximum)
voltage supervising along with on-the-fly adjustable watchdog timing in order to
monitor critical processing elements in systems.
Microcontroller Supply and
Watchdog Monitoring Circuit
Design Requirements
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Detailed Design Procedure
Setting the Voltage Threshold
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.
Meeting the Watchdog Timeout Period
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.
Setting the Reset Delay
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.
Setting the Startup Delay and Output Topology
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.
Calculating the RESET Pullup Resistor
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.
Open-Drain RESET Configuration
Design 1: Monitoring a Microcontroller Supply Voltage and Watchdog Timer
The TPS35-Q1 features high-accuracy (1.2% maximum)
voltage supervising along with on-the-fly adjustable watchdog timing in order to
monitor critical processing elements in systems.
Microcontroller Supply and
Watchdog Monitoring Circuit
The TPS35-Q1 features high-accuracy (1.2% maximum)
voltage supervising along with on-the-fly adjustable watchdog timing in order to
monitor critical processing elements in systems.
Microcontroller Supply and
Watchdog Monitoring Circuit
The TPS35-Q1 features high-accuracy (1.2% maximum)
voltage supervising along with on-the-fly adjustable watchdog timing in order to
monitor critical processing elements in systems.
Microcontroller Supply and
Watchdog Monitoring Circuit
Microcontroller Supply and
Watchdog Monitoring Circuit
Design Requirements
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Design Requirements
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Design Parameters
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
PARAMETER
DESIRED REQUIREMENT
DESIGN RESULT
PARAMETER
DESIRED REQUIREMENT
DESIRED REQUIREMENT
DESIGN RESULT
DESIGN RESULT
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Threshold Voltage
Threshold Voltage
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Typical threshold voltage of 1.65 V
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
Watchdog Timeout Period
Watchdog Timeout Period
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
Typical timeout period of 1.6 s
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
RESET Delay
RESET Delay
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Typical reset delay of 200 ms
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Startup Delay
Startup Delay
Minimum startup delay of 700 ms
Minimum startup delay of 700 ms
Minimum startup delay of 900 ms
Minimum startup delay of 900 ms
Output Logic
Open-drain
Open-drain
Output Logic
Output Logic
Open-drain
Open-drain
Open-drain
Open-drain
Maximum Device Current Consumption
20 μA
250 nA typical, 3 μA maximum
Maximum Device Current Consumption
Maximum Device Current Consumption
20 μA
20 μA
250 nA typical, 3 μA maximum
250 nA typical, 3 μA maximum
Detailed Design Procedure
Setting the Voltage Threshold
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.
Meeting the Watchdog Timeout Period
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.
Setting the Reset Delay
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.
Setting the Startup Delay and Output Topology
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.
Calculating the RESET Pullup Resistor
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.
Open-Drain RESET Configuration
Detailed Design Procedure
Setting the Voltage Threshold
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.
Setting the Voltage Threshold
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.
The negative-going threshold voltage, VIT-, is set by the device variant. #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB shows how to calculate the "Threshold Voltage" section of the orderable part number.IT-#GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05
OPN "Threshold
Voltage" number = (VIT- - 1) /
0.05IT-In this example, the nominal supply voltage for
the microcontroller is 1.8 V. The minimum supply voltage is 10% lower than the
nominal supply voltage, or 1.62 V. Setting a 1.65 V threshold ensures that the
device will be reset just before the supply voltage reaches the minimum allowed.
Thus a 1.65 V threshold is chosen and, using #GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTB, the part number
is reduced to TPS35xx13xxxxxxxQ1. Since the
hysteresis is 5% typical, the positive-going threshold voltage, VIT+, is
1.73 V.#GUID-D42EE85E-B904-4EDB-8CC9-1CD90C625CBE/EQUATION-BLOCK_XV1_5Z1_YTBQ1IT+
Meeting the Watchdog Timeout Period
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.
Meeting the Watchdog Timeout Period
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.
The watchdog timeout design requirement can be met
either by using a fixed-timeout version of the TPS35-Q1 or by
connecting a capacitor between the CWD pin and GND. The typical values can be met
with preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for
a list of fixed timeouts. If using the CWD feature, pinout A or B must be used;
please refer to
tWD Timer
for instructions
on how to program the timout period. The design requirement in this example is
tWD = 1.6 s. This is one of the fixed timeout options offered by
pinout C or D. Thus the possible variant
option is narrowed down to TPS35Cx13KAxDDFRQ1.TPS35-Q1Timing Requirements
tWD Timer
tWD TimerWDWD or DTPS35Cx13KAxDDFRQ1
Setting the Reset Delay
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.
Setting the Reset Delay
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.
The reset delay requirement can be met either by
using a fixed-timeout version of the TPS35-Q1 or by connecting a
capacitor between the CRST pin and GND. The typical values can be met with
preprogrammed fixed time options, hence a pinout offering fixed time options is
selected. Please see the Timing Requirements for a list of fixed timeouts. If using
the CRST feature, pinout A or B must be used; please refer to the Timing
Specifications for instructions on how to program the timout period. The
design requirement in this example is tD = 200 ms. Thus the possible
variant option is narrowed down to TPS35Cx13KAGDDFRQ1.TPS35-Q1Timing
SpecificationsDTPS35Cx13KAGDDFRQ1
Setting the Startup Delay and Output Topology
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.
Setting the Startup Delay and Output Topology
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.
The startup delay and output topology are set by
the device variant. Please refer to Device Comparison for the possible
options. A minimum startup delay of 700 ms and
open-drain output are desired, thus Option D, 1 s
typical startup delay and open-drain active-low,
is selected. Thus the option suitable to meet
design requirements is TPS35CD13KAGDDFRQ1.Device ComparisonTPS35CD13KAGDDFRQ1
Calculating the RESET Pullup Resistor
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.
Open-Drain RESET Configuration
Calculating the RESET Pullup Resistor
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.
Open-Drain RESET Configuration
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.
Open-Drain RESET Configuration
The TPS35-Q1 uses an open-drain configuration for the RESET output, as shown in . When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET pulls the output to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that VOL is below its maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (VPU), the recommended maximum RESET pin current (IRST), and VOL. The maximum VOL is 0.3 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.3 V with IRST kept below 2 mA for VDD ≥ 3 V and 500 μA for VDD = 1.5 V. For this example, with a VPU =VDD = 1.5 V, a resistor must be chosen to keep IRST below 500 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 10 kΩ was selected, which sinks a maximum of 180 μA when RESET is asserted.TPS35-Q1RESETOLPURESETRSTOLOLRSTDDDDPUDDRSTRESET
Open-Drain RESET Configuration
Open-Drain RESET Configuration
Open-Drain RESET ConfigurationRESET
Power Supply Recommendations
This device is designed to operate from
an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is
not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin.
Power Supply Recommendations
This device is designed to operate from
an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is
not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin.
This device is designed to operate from
an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is
not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin.
This device is designed to operate from
an input supply with a voltage range between 1.04 V and 6 V. An input supply capacitor is
not required for this device; however, if the input supply is noisy, then good analog
practice is to place a 0.1-µF capacitor between the VDD pin and the GND pin.
Layout
Layout Guidelines
Make sure that the connection to the VDD pin is
low impedance. Good analog design practice recommends placing a 0.1-µF ceramic
capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the
RESET
delay time is not adversely affected.
Make sure that the connection
to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
Place CCRST
capacitor as close as possible to the CRST pin.
Place CCWD
capacitor as close as possible to the CWD pin.
Place the pullup resistor on
the
RESET
pin as close to the pin as
possible.
Layout Example
Typical
Layout for the Pinout C of TPS35-Q1
Layout
Layout Guidelines
Make sure that the connection to the VDD pin is
low impedance. Good analog design practice recommends placing a 0.1-µF ceramic
capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the
RESET
delay time is not adversely affected.
Make sure that the connection
to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
Place CCRST
capacitor as close as possible to the CRST pin.
Place CCWD
capacitor as close as possible to the CWD pin.
Place the pullup resistor on
the
RESET
pin as close to the pin as
possible.
Layout Guidelines
Make sure that the connection to the VDD pin is
low impedance. Good analog design practice recommends placing a 0.1-µF ceramic
capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the
RESET
delay time is not adversely affected.
Make sure that the connection
to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
Place CCRST
capacitor as close as possible to the CRST pin.
Place CCWD
capacitor as close as possible to the CWD pin.
Place the pullup resistor on
the
RESET
pin as close to the pin as
possible.
Make sure that the connection to the VDD pin is
low impedance. Good analog design practice recommends placing a 0.1-µF ceramic
capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the
RESET
delay time is not adversely affected.
Make sure that the connection
to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
Place CCRST
capacitor as close as possible to the CRST pin.
Place CCWD
capacitor as close as possible to the CWD pin.
Place the pullup resistor on
the
RESET
pin as close to the pin as
possible.
Make sure that the connection to the VDD pin is
low impedance. Good analog design practice recommends placing a 0.1-µF ceramic
capacitor as near as possible to the VDD pin. If a capacitor is not connected to the
CRST pin, then minimize parasitic capacitance on this pin so the
RESET
delay time is not adversely affected.
Make sure that the connection
to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
Place CCRST
capacitor as close as possible to the CRST pin.
Place CCWD
capacitor as close as possible to the CWD pin.
Place the pullup resistor on
the
RESET
pin as close to the pin as
possible.
RESET
RESET
Make sure that the connection
to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.
Place CCRST
capacitor as close as possible to the CRST pin.
Place CCWD
capacitor as close as possible to the CWD pin.
Place the pullup resistor on
the
RESET
pin as close to the pin as
possible.
Make sure that the connection
to the VDD pin is low impedance. Good analog design practice is to place a
0.1-µF ceramic capacitor as near as possible to the VDD pin.Place CCRST
capacitor as close as possible to the CRST pin.CRSTPlace CCWD
capacitor as close as possible to the CWD pin.CWDPlace the pullup resistor on
the
RESET
pin as close to the pin as
possible.
RESET
RESET
Layout Example
Typical
Layout for the Pinout C of TPS35-Q1
Layout Example
Typical
Layout for the Pinout C of TPS35-Q1
Typical
Layout for the Pinout C of TPS35-Q1
Typical
Layout for the Pinout C of TPS35-Q1
Typical
Layout for the Pinout C of TPS35-Q1
TPS35-Q1
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Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
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Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
TI Glossary
TI GlossaryThis glossary lists and explains terms, acronyms, and definitions.
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Copyright © 2023, Texas Instruments Incorporated for the tD value computation. For a capacitor based tD delay option, the RESET will be asserted for tSTRT + 2 msec time if the CRST pin is open.
Device pinout options A to C offer only RESET output. In these devices the internal RESET output from supervisor and WDO output from watchdog timer are ANDed together to drive the external RESET output.
The supervisor offers wide range of fixed
monitoring thresholds (VIT-) from 1.05 V to 5.40 V in steps of 50 mV. The
device asserts the RESET output when the VDD signal falls below VIT-
threshold. The device offers hysteresis functionality for voltage supervision. This
ensures the supply has recovered above the monitoring threshold before the RESET
output is deasserted. The TPS35-Q1 typical voltage hysteresis
(VHYS) is 5%. Along with the voltage hysteresis, the device keeps the
RESET output asserted for time duration tD after the supply has risen
above VIT+. The RESET output assert duration changes from tD
to tSTRT + tD if the VDD signal is ramping from voltage <
VPOR. The tD time duration can be programmable using an
external capacitor or fixed time options offered by the device.
The typical timing behavior for a voltage
supervisor and the RESET output is showcased in Figure 8-5. The voltage
supervisor monitoring output has higher priority over watchdog functionality. If the
device voltage supervisor output is asserted, the watchdog functionality will be
disabled including WDO assert control. The device resumes watchdog related
functionality only after the supply is stable and the tD time duration
has elapsed.
Figure 8-5 Voltage Supervisor Timing Diagram