SPRS288H May   2008  – October 2021


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. VDD Hysteresis
        2. VDD Glitch Immunity
      2. 7.3.2 Implemented Window-Watchdog Settings
        1. Timing Rules of Window-Watchdog
      3. 7.3.3 Watchdog Software Considerations
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Lower-Boundary Calculation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Programming Window-Watchdog Using an External Capacitor
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


The TPS3813-Q1 supervisory circuits provide circuit initialization and timing supervision, primarily for DSPs and processor-based systems.

During power on, the RESET pin is asserted when the supply voltage (VDD) becomes higher than 1.1 V. Thereafter, the supervisory circuit monitors VDD and keeps the RESET pin active as long as VDD remains below the threshold voltage (VIT).

An internal timer delays the return of the output to the inactive (high) state to ensure proper system reset. The delay time, td = 25 ms typical, begins after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by an internal voltage divider.

For safety-critical applications, the TPS3813-Q1 family of devices incorporate a window-watchdog with programmable delay and window ratio. The upper limit of the watchdog time-out can be set by either connecting the WDT pin to GND or VDD, or by using an external capacitor. The lower limit, and thus the window ratio, is set by connecting the WDR pin to GND or VDD. The RESET pin will assert a reset to the microcontroller if the watchdog is incorrectly serviced.

The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The devices are available in a 6-pin SOT-23 package. The devices are characterized for operation over a temperature range of –40°C to 125°C.

Device Information
TPS3813K33-Q1SOT-23 (6)2.90 mm × 1.60 mm
For all available packages, see the orderable addendum at the end of the data sheet.
GUID-C28894AE-EA1A-48BA-9988-4F17CE282557-low.gif Typical Operating Circuit