SPRS288H May   2008  – October 2021

PRODMIX  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Glitch Immunity
      2. 7.3.2 Implemented Window-Watchdog Settings
        1. 7.3.2.1 Timing Rules of Window-Watchdog
      3. 7.3.3 Watchdog Software Considerations
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Lower-Boundary Calculation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Window-Watchdog Using an External Capacitor
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

VDD Glitch Immunity

These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on both pulse duration (tGI_VIT) found in Section 6.6 and transient overdrive. Overdrive is defined by how much VDD exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 1.

Equation 1. Overdrive = | ((VDD / VIT) – 1) × 100% |

where

  • VIT = VIT– is the threshold voltage
  • VIT+ = VIT + VHYS is the rising threshold voltage
  • VDD is the input voltage crossing VIT
GUID-765EA975-312B-4CBC-A4A2-44F774CE2600-low.gifFigure 7-1 Overdrive Versus Pulse Duration

TPS3813-Q1 devices have built-in glitch immunity (tGI_VIT-) as shown in Section 6.6. Figure 7-1 shows that VDD must fall below VIT for tGI_VIT, otherwise the faling transistion is ignored. When VDD falls below VIT for tGI_VIT, RESET transitions low to indicate a fault condition after the propagation delay high-to-low (tPHL). When VDD rises above VIT+ = VIT + VHYS, RESET deasserts to a logic high indicating there is no more fault condition only if VDD remains above VIT+ for longer than the reset delay (tD).