SLVS331I December   2000  – October 2021

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
    1.     6
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Dissipation Ratings
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Glitch Immunity
      2. 8.3.2 User-Programmable Watchdog Timer (WDI)
      3. 8.3.3 RESET Output
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VIT)
      2. 8.4.2 Above Power-On Reset But Less Than Threshold (VPOR < VDD < VIT)
      3. 8.4.3 Below Power-On Reset (VDD < VPOR)
    5. 8.5 Programming
      1. 8.5.1 Implementing Window-Watchdog Settings
      2. 8.5.2 Programmable Window-Watchdog by Using an External Capacitor
      3. 8.5.3 Lower Boundary Calculation
      4. 8.5.4 Watchdog Software Considerations
      5. 8.5.5 Power-Up Considerations
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5.1 Implementing Window-Watchdog Settings

There are two ways to configure the watchdog timer window the most flexible is to connect a capacitor to WDT to set the upper boundary of the window watchdog while connecting WDR to either VDD or GND, thus setting the lower boundary. The other way to configure the timing is by wiring the WDT and WDR pin to either VDD or GND. By hardwiring the pins to either VDD or GND there are four different timings available; these settings are listed in Table 8-2.

Table 8-2 Cap-Free Timer Settings
SELECTED OPERATION MODEWINDOW FRAMELOWER WINDOW FRAME
WDT = 0 VWDR = 0 VMax = 0.3 sMax = 9.46 ms
Typ = 0.25 sTyp = 7.86 ms
Min = 0.2 sMin = 6.27 ms
WDR = VDDMax = 0.3 sMax = 2.43 ms
Typ = 0.25 sTyp = 2 ms
Min = 0.2 sMin = 1.58 ms
WDT = VDDWDR = 0 VMax = 3 sMax = 93.8 ms
Typ = 2.5 sTyp = 78.2 ms
Min = 2 sMin = 62.5 ms
WDR = VDDMax = 3 sMax = 23.5 ms
Typ = 2.5 sTyp = 19.6 ms
Min = 2 sMin = 15.6 ms

To visualize the values named in the table, a timing diagram was prepared. It is used to describe the upper and lower boundary settings. For an application, the important boundaries are the tboundary,max and twindow,min. Within these values, the watchdog timer must be retriggered to avoid a time-out condition or a boundary violation in the event of a trigger pulse in the lower boundary. The values in the table above are typical and worst-case conditions. They are valid over the whole temperature range of –40°C to +85°C.

In the shaded area of Figure 8-2, it cannot be predicted if the device detects a violation or not and release a reset. This is also the case between the boundary tolerance of tboundary,min and tboundary,max as well as between twindow,min and twindow,max. It is important to set up the trigger pulses accordingly to avoid violations in these areas.

GUID-3E312953-00F9-47A7-A774-26B20299B79B-low.gif Figure 8-2 Upper and Lower Boundary Visualization