SNVSB03D December 2018 – January 2020 TPS3840
RESET (active-high), denoted with no bar above the pin label, applies only to TPS3840PH push-pull active-high version. RESET remains low (deasserted) as long as VDD is above the threshold (VIT-) and the manual reset signal (MR) is logic high or floating. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then RESET is asserted driving the RESET pin to high voltage (VOH).
When MR is again logic high and VDD is above VIT+ the delay circuit will hold RESET high for the specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to low voltage (VOL )