SNVSB03D December 2018 – January 2020 TPS3840
RESET (Active-Low) applies to TPS3840DL (Open-Drain) and TPS3840PL (Push-Pull) hence the "L" in the device name. RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT-) and the MR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then RESET is asserted.
When MR is again logic high or floating and VDD rise above VIT+, the delay circuit will hold RESET low for the specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic high voltage (VOH).
The TPS3840DL (Open-Drain) version, denoted with "D" in the device name, requires a pull-up resistor to hold RESET pin high. Connect the pull-up resistor to the desired pull-up voltage source and RESET can be pulled up to any voltage up to 10 V independent of the VDD voltage. To ensure proper voltage levels, give some consideration when choosing the pull-up resistor values. The pull-up resistor value determines the actual VOL, the output capacitive loading, and the output leakage current (ILKG(OD)).
The Push-Pull variants (TPS3840PL and TPS3840PH), denoted with "P" in the device name, does not require a pull-up resistor