SBVS300A November 2016 – September 2021 TPS3851
Forcing a RESET is dependent on two conditions: the amplitude VDD is beyond the trip point (ΔV1 and ΔV2), and the length of time that the voltage is beyond the trip point (t1 and t2). If the voltage is just under the trip point for a long period of time, RESET asserts and the output is pulled low. However, if VDD is just under the trip point for a few nanoseconds, RESET does not assert and the output remains high. The length of time required for RESET to assert can be changed by increasing the amount VDD goes under the trip point. If VDD is under the trip point by 10%, the amount of time required for the comparator to respond is much faster and causes RESET to assert much quicker than when barely under the trip point voltage. Equation 3 shows how to calculate the percentage overdrive.
In Equation 3, VITX corresponds to the threshold trip point. If VDD is
exceeding the positive threshold,
VITN + VHYST is used. VITN is used when VDD is falling below the negative threshold. In Figure 8-2, t1 and t2 correspond to the amount of time that VDD is over the threshold; the propagation delay versus overdrive for VITN and VITN + VHYST is illustrated in Figure 6-16 and Figure 6-18, respectively.
The TPS3851 is relatively immune to short positive and negative transients on VDD because of the overdrive voltage curve.