SLVSA75A July   2010  – August 2015 TPS386596

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Monitoring
      2. 8.3.2 Manual Reset
      3. 8.3.3 Reset Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Undervoltage Detection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Spice Models
      2. 12.1.2 Device Nomenclature
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DGK Package
8-Pin VSSOP
Top View
TPS386596 PinOut_lvsa75.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GND 5 — Ground
MR 7 I Manual reset input with internal 100-kΩ pullup to VDD and 50-ns deglitch. Logic low level of this pin asserts RESET.
RESET 6 O RESET is an open-drain output pin. When RESET is asserted, this pin remains in a low-impedance state. When RESET is deasserted, this pin goes to a high-impedance state after 50 ms. A pullup resistor to VDD or another voltage source is required.
SENSE1 4 I Monitor voltage input for Supply 1 When the voltage at this terminal drops the threshold voltage (VIT1= 2.9 V), RESET is asserted.
SENSE2 3 I Monitor voltage input for Supply 2 When the voltage at this terminal drops the threshold voltage (VIT2= 0.4 V), RESET is asserted.
SENSE3 2 I Monitor voltage input for Supply 3 When the voltage at this terminal drops the threshold voltage (VIT3= 0.4 V), RESET is asserted.
SENSE4 1 I Monitor voltage input for Supply 4 When the voltage at this terminal drops the threshold voltage (VIT4= 0.4 V), RESET is asserted.
VDD 8 I Supply voltage. Connecting a 0.1-µF ceramic capacitor close to this pin is recommended.