SNVSBT6C July   2021  – December 2022 TPS38700-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
      1.      Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

I2C

Refer to Table 8-1 for the I2C register map overview. Note that "PSEQ" refers to TPS38700-Q1 and is used enhance table readability.

Table 8-1 I2C Register Categories and Associated Details
TYPEBITSDESCRIPTIONRANGE / FUNCTION OR STATUSWHO TOGGLES THEM?WHO ELSE CAN WRITE TO THEM?WHAT GETS AFFECTED DUE TO THIS BIT?
OTP bits RVENDORID[7:0]TI definedTI definedOTP optionNoneNone
MODEL_REV[7:0]TI definedTI definedOTP optionNoneNone
TARGET_ID[7:0]TI definedTI definedOTP optionNoneI2C
Interrupt info bits RW1CF_INTERRInternal faultNo internal fault / Internal fault detectedInterruptAny of the interrupts generated; Can be cleared by writing 1NIRQ
EM_PD (1)Emergency Power downNo emergency PD / shutdown caused by emergency PDPSEQPSEQ; SOCNRST; NIRQ
WDTWatchdog violationDid not occur / occurredWatchdogWD; SOCNIRQ; NRST (depends on if set in configuration register)
F_PECPacket Error checking (PEC)PEC miscompare did not occur / occurredI2CI2C; SOCNIRQ
RTCRTC alarmhas not triggered / triggeredRTCRTC; SOCNIRQ
F_ENEnable output pin faultNo faults detected / fault detectedEN readback-PSEQPSEQ; SOCNIRQ; NRST
F_OSCCrystal oscillator faultNo faults detected / fault detectedFrequency detectorFrequency detector; SOCNIRQ
F_NRSTIRQReset or Interrupt pin faultNo faults detected / fault detectedReset readback-PSEQPSEQ; SOCNIRQ
F_BISTBuilt-In self test faultNo faults detected / fault detectedBISTBIST; SOCNIRQ; NRST
F_LDOLDO faultNo faults detected / fault detectedBISTBIST; SOCNIRQ; NRST
F_TSDThermal shutdown faultNo faults detected / fault detectedTSDTSD; SOCNIRQ; NRST
F_RT_CRCRuntime CRC register faultNo faults detected / fault detectedCRCSOCNIRQ
F_ECC_DEDECC double error deduction on OTP loadNo ECC DED / ECC DED on OTP loadNVM_ECC; REG_CRCNVM_ECC; REG_CRC; SOCNIRQ; NRST
F_PBSB (1)NPWR_BTN short pressNo short pulse / short pulsePSEQPSEQ; SOCNRST; NIRQ
Status bits RST_NIRQCurrent state of NIRQ outputNIRQ asserted / not assertedInterruptNoneNone
ST_NRSTCurrent state of NRST outputNRST asserted / not assertedInterrupt; NRSTstate changeNoneNone
ST_ACTSLPCurrent state of SLEEP inputSLEEP pin driven Low or HighPSEQNoneNone
ST_ACTSHDNCurrent state of ACT inputACT pin driven Low or HighPSEQNoneNone
ST_PSEQ[1:0]Current state of PSEQSHDNx, Power Up, Power Down, Sleep, Sleep entry, Sleep exit, invalid, ActivePSEQNoneNone
STDR1Current drive state of EN12 to EN9Sequencer is driving EN Low or HighPSEQNoneNone
STDR2Current drive state of EN8 to EN1Sequencer is driving EN Low or HighPSEQNoneNone
OPENWatchdog Open WindowWatchdog update Window closed / openWDNoneNone
WDUVWatchdog Update ViolationNo violation / WD updated too earlyWDNoneNone
WDEXPWatchdog close timer expiredWDT not expired / expiredWDNoneNone
BIST_CBIST stateBIST not complete or executed / BIST completeBISTNoneNone
ECC_SECStatus of ECC single error correctionNo error correction applied / SEC appliedNVM_ECCNoneNone
BIST_VMStatus of volatile memory test output from BISTVolatile memory test pass / failREG_CRCNoneNone
BIST_NVMStatus of non-volatile memory test output from BISTNon-Volatile memory test pass / failOTP coveredNoneNone
BIST_LStatus of Logic test ouput from BISTLogic test pass / failBISTNoneNIRQ/ NRST
BIST_AStatus of Analog test ouput from BISTAnalog test pass / failBISTNoneNIRQ/ NRST
OTP bits REN_AF[12:9]Enable AF for EN12, EN11, EN10, EN9Disabled/ EnabledOTP optionNonePSEQ
AFIO[12:9]Select AF for EN12, EN11, EN10, EN9GPO or NPWR_BTN /NRST_IN/ NEM_PDOTP optionNonePSEQ
PP_EN[12:1]ENx pin driver configurationOpen drain/ Push-PullOTP optionNoneIO
XTAL_LOADCrystal oscillator load capacitanceExternal/ InternalOTP optionNoneXTAL
XTAL_ENCrystal oscillator EnableCrystal driver disabled/ enabledOTP optionNoneXTAL
PP_CLK32KCLK32K pin driver configurationOpen drain/ Push-PullOTP optionNoneXTAL
CONTROL R/WGPIO[12:9]General purpose input / outputsOpen drain / Push-PullSOCNonePSEQ
Debounce[3:0]Debounce value for AF input pins5 ms to 80 msSOCNonePSEQ
EN_DEB[12:9]Enable debounce for AF input pinsDebouce disabled / enabledSOCNonePSEQ
LP_TIME_TSHLD[7:0]NPWR_BTN long press time threshold100 ms to 25.6 s SOCNonePSEQ
RELOADReload OTPReload or do not Reload when SEQ5 / 6 is completeSOCSOCOTP Register
FORCE_INTForce NIRQ lowNIRQ contolled by faults / registerSOCSOCNRST
FORCE_ACTForce PSEQ Active stateSLEEP pin controls exit / entry or is ignoredPSEQSOC can clear it; but not set itPSEQ
FORCE_SHDN[1:0]Force PSEQ Shutdown stateACT pin control or Force SHDN and resume ACT pin control after delaySOCSOC; WDTPSEQ
RST_DLY[3:0]Reset Delay0.1 ms to 128 msSOCNonePSEQ
RTC_WAKEAutonomous wake alarm enableDisabled / EnabledSOCNoneRTC
RTC_PUAutonomous RTC power up from SHDN2 to ACTIVEDisabled / EnabledSOCNoneRTC
REQ_PECRequire PEC byte (if EN_PEC = 1)Missing PEC is treated as good / badSOCNoneI2C
EN_PECPacket Error checking (PEC)PEC disabled / enabledSOCNoneI2C
AT_PORRun BIST at PORSkip / run BIST at PORSOCNoneBIST
AT_SHDNRun BIST when exiting SEQ5 / 6Default to not run BISTSOCNoneBIST
PSEQUSLOT[3:0]Power Up / Sleep Exit time slots125 μs / 2.5 sSOCNonePSEQ
DSLOT[3:0]Power down / Sleep Entry time slots125 μs / 2.5 sSOCNonePSEQ
SSTEPSlot step multiplier250 μs / 1000 μsSOCNonePSEQ
PU[3:0][12:1]Power Up SequenceENx not mapped / ENx mapped SOCNonePSEQ
PD[3:0][12:1]Power Down SequenceENx not mapped / ENx mapped SOCNonePSEQ
SLP_EXT[3:0][12:1]Sleep Exit SequenceENx not mapped / ENx mappedSOCNonePSEQ
SLP_ENTRY[3:0][12:1]Sleep Entry SequenceENx not mapped / ENx mapped SOCNonePSEQ
RTC (2)RTC_T[31:0]RTC time setting1 sec to 136 yearsXTAL; internal oscillatorNoneRTC
RTC_A[31:0]RTC alarm setting1 sec to 136 yearsSOCNoneRTC
WDTWDT_EN[1:0]Watchdog configurationDisabled / EnabledSOCNoneWDT
SLP_ENAutomatic disable in Sleep modeWatchdog disabled / enabled in SleepSOCNoneWDT
WDT_DLY[2:0]Delay in number of Watchdog periods1 or 8 WDT periodSOCNoneWDT
PDMD[1:0]Power down mode for WDT force power downValue written to CTL_1.FORCE_SHDN on WDT power downSOCNonePSEQ
CLOSE[7:0]WDT close window configuration1 ms to 864 msSOCNoneWDT
OPEN[7:0]WDT open window configuration1 ms to 864 msSOCNoneWDT
KEY[7:0]WDT key to reset0 / 1SOCNoneWDT
PROTWRKWork set register lock0 / 1SOC only 1NoneWrite function to those register groups
SEQSSEQS set register lock0 / 1SOC only 1NoneWrite function to those register groups
SEQPSEQP set register lock0 / 1SOC only 1NoneWrite function to those register groups
SEQCSEQC set register lock0 / 1SOC only 1NoneWrite function to those register groups
WDTWDT set register lock0 / 1SOC only 1NoneWrite function to those reg groups
RTCRTC set register lock0 / 1SOC only 1NoneWrite function to those reg groups
CTLCTL set register lock0 / 1SOC only 1NoneWrite function to those reg groups
Presence of fault reporting functionality dependent on part configuration.
Register RTC_T must be written to before writing a value in register RTC_A.
Figure 8-17 I2C Single Byte Write.
Figure 8-18 I2C Single Byte Read.
Figure 8-19 I2C Sequencial Write.
Figure 8-20 I2C Sequential Read.
Figure 8-21 I2C Single Byte Write with PEC.
Figure 8-22 I2C Single Byte Read with PEC.