SLVSG89B April   2021  – January 2024 TPS3899-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Hysteresis
      2. 7.3.2 User-Programmable Sense and Reset Time Delay
      3. 7.3.3 RESET/RESET Output
      4. 7.3.4 SENSE Input
        1. 7.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

The primary constraint for this application is choosing the correct device to monitor the supply voltage of the microprocessor. The TPS3899-Q1 can monitor any voltage with the adjustable voltage threshold option or fixed voltages between 0.8V and 5.4V. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct voltage supervisor variant to choose. In this example,
Figure 8-2 shows the output, RESET, of the TPS3899DL01-Q1 when the 3.3V rail falls to 2.9V after the sense time delay expires. The TPS3899PL16-Q1 triggers a reset when the 1.8V rail falls to 1.6V.

The secondary constraint for this application is the sense and reset time delay. If the monitored voltage rail 3.3V has large voltage ripple noise and goes below the programmed threshold voltage but returns above the
VIT-+ VHYS before the sense time delay expires, the output does not assert. Therefore, the sense time delay prevents false sense resets by allowing the monitored voltage rail 3.3V to not assert the output during the programmed sense time delay period set by the capacitor on the CTS pin. In the application, the CTS capacitors for both the TPS3899DL01-Q1 and TPS3899PL16-Q1 are set to be 0.022μF and 0.01μF, respectively, and resulted in sense time delays of 13.7ms and 6.2ms. In addition to the sense delay time, the reset time delay for the TPS3899DL01-Q1 must be at least 25ms to allow the microprocessor, and all other devices using the 3.3V rail, enough time to startup correctly before the 1.8V rail is enabled via the LDO. Once the LDO is enabled, the reset time delay for the TPS3899PL16-Q1 must be at least 10ms to allow the 1.8V rail to settle. For applications with ambient temperatures ranging from –40°C to +125°C, CTS and CTR can be calculated using RCTS and RCTR. Solving for CCTS and CCTR in Equation 4 and Equation 5 for 10ms and 25ms gives a minimum capacitor value of 0.016µF and 0.0403µF which are rounded up to standard values of 0.022µF and 0.047µF, respectively, to account for capacitor tolerance.

GUID-20210312-CA0I-T7WM-HRG1-NTBJFZQLS9QZ-low.svg Figure 8-2 TPS3899DL01-Q1 3.3V Voltage Rail Monitor Timing Diagram

A 1µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor is only required for the open-drain device variants and is calculated to make sure that VOL does not exceed the max limit given the IRESET(Sink) possible at the expected supply voltage. The open-drain variant is used in this design example and the nominal VDD is 3.3V but dropping to 2.9V for VIT-, the voltage across the pull-up resistor can be determined. In Section 6.5, max VOL provides 2mA IRESET(Sink) for 3.3V VDD. Using 2mA of IRESET(Sink) and 300mV max VOL, gives us 1.3kΩ for the pull-up resistor. Any value higher than 1.3kΩ makes sure that VOL does not exceed the 300mV max specification.