SLVSG89B April   2021  – January 2024 TPS3899-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Nomenclature
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 VDD Hysteresis
      2. 7.3.2 User-Programmable Sense and Reset Time Delay
      3. 7.3.3 RESET/RESET Output
      4. 7.3.4 SENSE Input
        1. 7.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VDD(min))
      2. 7.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 7.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Dual Rail Monitoring with Power-Up Sequencing
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Timing Requirements

At 0.85 V ≤ VDD ≤ 6 V, CTR = CTS = Open, RESET pull-up resistor (Rpull-up) = 100 kΩ to VDD, output reset load 
(CLOAD) = 10 pF and over the operating free-air temperature range –40°C to 125°C, unless otherwise noted.
VDD ramp rate ≤ 1 V / µs. Typical values are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tSTRT Startup Delay (1) CTR pin = Open or NC 300 µs
tD-SENSE Detect time delay
VDD = (VIT+ + 10%) to (VIT- – 10%) (2)		 CTS pin = Open or NC
 		 30 50 µs
CTS pin = 10 nF
 		 6.2 ms
CTS pin = 1 µF
 		 619 ms
tD Reset time delay CTR pin = Open or NC 40 80 µs
CTR pin = 10 nF (3) 6.2 ms
CTR pin = 1 µF (3) 619 ms
tGI_VIT- Glitch immunity VIT- 5% VIT- overdrive (4) 10 µs
(1) When VDD starts from less than VPOR and then exceeds the specified minimum VDD, reset is asserted till startup delay (tSTRT) + tD delay based on capacitor on CTR pin. After this time, the device controls the RESET pin based on the SENSE pin voltage.
(2) tD_SENSE measured from threhold trip point (VIT-) to VOL for active low variants and VOH for active high variants. 
(3) Ideal capacitor
(4) Overdrive % = [(VDD/ VIT-) - 1] × 100%