SLUSEE5D January   2022  – April 2024 TPS4811-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Charge Pump and Gate Driver output (VS, PU, PD, BST, SRC)
      2. 8.3.2  Capacitive Load Driving
        1. 8.3.2.1 FET Gate Slew Rate Control
        2. 8.3.2.2 Using Precharge FET - (with TPS48111-Q1 Only)
      3. 8.3.3  Short-Circuit Protection
        1. 8.3.3.1 Overcurrent Protection With Auto-Retry
        2. 8.3.3.2 Overcurrent Protection With Latch-Off
      4. 8.3.4  Short-Circuit Protection
      5. 8.3.5  Analog Current Monitor Output (IMON)
      6. 8.3.6  Overvoltage (OV) and Undervoltage Protection (UVLO)
      7. 8.3.7  Device Functional Mode (Shutdown Mode)
      8. 8.3.8  Remote Temperature sensing and Protection (DIODE)
      9. 8.3.9  Output Reverse Polarity Protection
      10. 8.3.10 TPS4811x-Q1 as a Simple Gate Driver
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Driving HVAC PTC Heater Load on KL40 Line in Power Distribution Unit
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application: Driving B2B FETs With Pre-charging the Output Capacitance
      1. 9.3.1 Design Requirements
      2. 9.3.2 External Component Selection
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2.1 FET Gate Slew Rate Control

For limiting inrush current during turn ON of the FET with capacitive loads, use R1, R2, C1 as shown in Figure 8-6. The R1 and C1 components slow down the voltage ramp rate at the gate of the FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.

GUID-20230127-SS0I-JHT9-XLGG-NRFXCT8SFKGP-low.svgFigure 8-6 Inrush Current limiting

Use the Equation 6 to calculate the inrush current during turn-ON of the FET.

Equation 2. GUID-20220922-SS0I-PZVR-0105-92TCVZNCGFX0-low.svg
Equation 3. GUID-20220112-SS0I-43BN-RHN3-JJ3TQM6HNLMV-low.svg

Where,

CLOAD is the load capacitance, VBATT is the input voltage and Tcharge is the charge time, V(BST-SRC) is the charge pump voltage (11 V),

Use a damping resistor R2 (~ 10 Ω) in series with C1. Equation 3 can be used to compute required C1 value for a target inrush current. A 100 kΩ resistor for R1 can be a good starting point for calculations.

Connecting PD pin of TPS12000-Q1 directly to the gate of the external FET ensures fast turn OFF without any impact of R1 and C1 components.

C1 results in an additional loading on CBST to charge during turn ON. Use Equation 4 to calculate the required CBST value.

Equation 4. GUID-20220112-SS0I-V95F-BDX3-VNV3VMQDVZVV-low.svg

Where, Qg(total) is the total gate charge of the FET.