SLUS984C November   2009  – April 2018 TPS51200-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Standard DDR Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Sink and Source Regulator (VO Pin)
      2. 7.3.2 Reference Input (REFIN Pin)
      3. 7.3.3 Reference Output (REFOUT Pin)
      4. 7.3.4 Soft-Start Sequencing
      5. 7.3.5 Enable Control (EN Pin)
      6. 7.3.6 Powergood Function (PGOOD Pin)
      7. 7.3.7 Current Protection (VO Pin)
      8. 7.3.8 UVLO Protection (VIN Pin)
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 S3 and Pseudo-S5 Support
      2. 7.4.2 Tracking Startup and Shutdown
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 VTT DIMM Applications
        1. 8.2.1.1 Design Parameters
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 VIN Capacitor
          2. 8.2.1.2.2 VLDO Input Capacitor
          3. 8.2.1.2.3 Output Capacitor
          4. 8.2.1.2.4 Output Tolerance Consideration for VTT DIMM Applications
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design Example 1
        1. 8.2.2.1 Design Parameters
      3. 8.2.3 Design Example 2
        1. 8.2.3.1 Design Parameters
      4. 8.2.4 Design Example 3
        1. 8.2.4.1 Design Parameters
      5. 8.2.5 Design Example 4
        1. 8.2.5.1 Design Parameters
      6. 8.2.6 Design Example 5
        1. 8.2.6.1 Design Parameters
      7. 8.2.7 Design Example 6
        1. 8.2.7.1 Design Parameters
      8. 8.2.8 Design Example 7
        1. 8.2.8.1 Design Parameters
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.3 Thermal Considerations

Because the TPS51200-Q1 device is a linear regulator, the VO current flows in both source and sink directions, thereby dissipating power from the device. When the device is sourcing current, the voltage difference between VLDOIN and VO times IO (IIO) current becomes the power dissipation as shown in Equation 2.

Equation 2. TPS51200-Q1 q_pdiss_src_lus812.gif

In this case, if VLDOIN is connected to an alternative power supply lower than the VDDQ voltage, overall power loss can be reduced. For the sink phase, VO voltage is applied across the internal LDO regulator, and the power dissipation, PDISS_SNK can be calculated by Equation 3.

Equation 3. TPS51200-Q1 q_pdiss_snk_lus812.gif

Because the device does not sink and source current at the same time and the IO current may vary rapidly with time, the actual power dissipation must be the time average of the above dissipations over the thermal relaxation duration of the system. Another source of power consumption is the current used for the internal current control circuitry from the VIN supply and the VLDOIN supply. This can be estimated as 5 mW or less during normal operatiing conditions. This power must be effectively dissipated from the package.

Maximum power dissipation allowed by the package is calculated by Equation 4.

PPKG = (TJ(MAX) – TA(MAX)) / RθJA
Equation 4. TPS51200-Q1 q_p_pkg_SLUS984.gif

where

  • TJ(MAX) is 125°C
  • TA(MAX) is the maximum ambient temperature in the system
  • RθJA is the thermal resistance from junction to ambient

The thermal performance of an LDO depends on the printed circuit board (PCB) layout. The TPS51200-Q1 device is housed in a thermally-enhanced package that has an exposed die pad underneath the body. For improved thermal performance, this die pad must be attached to ground via thermal land on the PCB. This ground trace acts as a both a heatsink and heatspreader. The typical thermal resistance, RθJA, 52.06°C/W, is achieved based on a land pattern of 3 mm × 1,9 mm with four vias (0,33-mm via diameter, the standard thermal via size) without air flow (see Figure 34).

TPS51200-Q1 v08018_lus812.gifFigure 34. Recommend Land Pad Pattern for TPS51200-Q1
TPS51200-Q1 package_measure_slus812.gifFigure 35. Package Thermal Measurement

To further improve the thermal performance of this device, using a larger than recommended thermal land as well as increasing the number of vias helps lower the thermal resistance from junction to thermal pad. The typical thermal resistance from junction to thermal pad, RθJP, is 10.24°C/W (based on the recommend land pad and four standard thermal vias).