SLUSAE5G August   2011  – April 2021 TPS53355


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Infomation
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V LDO and VREG Start-Up
      2. 7.3.2 Adaptive On-Time D-CAP Control and Frequency Selection
      3. 7.3.3 Ramp Signal
      4. 7.3.4 Adaptive Zero Crossing
      5. 7.3.5 Power-Good
      6. 7.3.6 Current Sense, Overcurrent and Short Circuit Protection
      7. 7.3.7 Overvoltage and Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Soft Start, and Mode Selection
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Circuit Diagram with Ceramic Output Capacitors
        1. Design Requirements
        2. Detailed Design Procedure
          1. Custom Design With WEBENCH® Tools
          2. External Component Selection
          3. External Component Selection Using All Ceramic Output Capacitors
        3. Application Curves
      2. 8.2.2 Typical Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Component Selection
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQP|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Certain points must be considered before starting a layout work using the TPS53355.

  • The power components (including input/output capacitors, inductor and TPS53355) must be placed on one side of the PCB (solder side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines.
  • All sensitive analog traces and components such as VFB, PGOOD, TRIP, MODE and RF should be placed away from high-voltage switching nodes such as LL, VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components.
  • Place the VIN decoupling capacitors as close to the VIN and PGND pins as possible to minimize the input AC current loop.
  • Because the TPS53355 controls output voltage referring to voltage across VOUT capacitor, the top-side resistor of the voltage divider should be connected to the positive node of the VOUT capacitor. Connect the GND of the bottom side resistor to the GND pad of the device. The trace from these resistors to the VFB pin should be short and thin.
  • Place the frequency setting resistor (RF), OCP setting resistor (RTRIP) and mode setting resistor (RMODE) as close to the device as possible. Use the common GND via to connect them to GND plane if applicable.
  • Place the VDD and VREG decoupling capacitors as close as possible to the device. Make sure GND vias are provided for each decoupling capacitor and make the loop as small as possible.
  • The PCB trace defined as switch node, which connects the LL pins and high-voltage side of the inductor, should be as short and wide as possible.
  • Connect the ripple injection VOUT signal (VOUT side of the C1 capacitor in Figure 8-2) from the terminal of ceramic output capacitor. The AC coupling capacitor (C2 in Figure 8-2) should be placed near the device, and R7 and C1 can be placed near the power stage.
  • Use separate vias or trace to connect LL node to snubber, boot strap capacitor and ripple injection resistor. Do not combine these connections.