SLUSAE5G August 2011 – April 2021 TPS53355
From small-signal loop analysis, a buck converter using D-CAP™ mode can be simplified as shown in Figure 8-1.
The output voltage is compared with the internal reference voltage (ramp signal is ignored here for simplicity). The PWM comparator determines the timing to turn on the high-side MOSFET. The gain and speed of the comparator can be assumed high enough to keep the voltage at the beginning of each on cycle substantially constant.
For loop stability, the 0-dB frequency, ƒ0, defined below need to be lower than 1/4 of the switching frequency.
According to the equation above, the loop stability of D-CAPTM mode modulator is mainly determined by the capacitor's chemistry. For example, specialty polymer capacitors (SP-CAP) have an output capacitance in the order of several 100 µF and ESR in range of 10 mΩ. These makes ƒ0 on the order of 100 kHz or less, creating a stable loop. However, ceramic capacitors have an ƒ0 at more than 700 kHz, and need special care when used with this modulator. An application circuit for ceramic capacitor is described in Section 22.214.171.124.3.