SLUSAE5G August   2011  – April 2021 TPS53355


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings (1)
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Infomation
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 5-V LDO and VREG Start-Up
      2. 7.3.2 Adaptive On-Time D-CAP Control and Frequency Selection
      3. 7.3.3 Ramp Signal
      4. 7.3.4 Adaptive Zero Crossing
      5. 7.3.5 Power-Good
      6. 7.3.6 Current Sense, Overcurrent and Short Circuit Protection
      7. 7.3.7 Overvoltage and Undervoltage Protection
      8. 7.3.8 UVLO Protection
      9. 7.3.9 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Soft Start, and Mode Selection
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
      3. 7.4.3 Forced Continuous Conduction Mode
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
    2. 8.2 Typical Applications
      1. 8.2.1 Typical Application Circuit Diagram with Ceramic Output Capacitors
        1. Design Requirements
        2. Detailed Design Procedure
          1. Custom Design With WEBENCH® Tools
          2. External Component Selection
          3. External Component Selection Using All Ceramic Output Capacitors
        3. Application Curves
      2. 8.2.2 Typical Application Circuit
        1. Design Requirements
        2. Detailed Design Procedure
          1. External Component Selection
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQP|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information
External Component Selection Using All Ceramic Output Capacitors

When a ceramic output capacitor is used, the stability criteria in Equation 7 cannot be satisfied. The ripple injection approach as shown in Figure 8-2 is implemented to increase the ripple on the VFB pin and make the system stable. In addition to the selections made using steps 1 through step 6 in Section, the ripple injection components must be selected. The C2 value can be fixed at 1 nF. The value of C1 can be selected between 10 nF to 200 nF.

Equation 11. GUID-3F9AA5AA-ABA3-49CF-99A4-6A99E42FC90D-low.gif


  • N is the coefficient to account for L and COUT variation

N is also used to provide enough margin for stability. It is recommended N=2 for VOUT ≤ 1.8 V and N=4 for VOUT ≥ 3.3 V or when L ≤ 250 nH. The higher VOUT needs a higher N value because the effective output capacitance is reduced significantly with higher DC bias. For example, a 6.3-V, 22-µF ceramic capacitor may have only 8 µF of effective capacitance when biased at 5 V.

Because the VFB pin voltage is regulated at the valley, the increased ripple on the VFB pin causes the increase of the VFB DC value. The AC ripple coupled to the VFB pin has two components, one coupled from SW node and the other coupled from the VOUT pin and they can be calculated using Equation 12 and Equation 13 when neglecting the output voltage ripple caused by equivalent series inductance (ESL).

Equation 12. GUID-142EF071-A4B1-4087-B968-4E442A189BCA-low.gif
Equation 13. GUID-FACC106C-EC1C-41D6-931C-E96666584C64-low.gif

It is recommended that VINJ_SW to be less than 50 mV and VINJ_TOTAL to be less than 60 mV. If the calculated VINJ_SW is higher than 50 mV, then other parameters need to be adjusted to reduce it. For example, COUT can be increased to satisfy Equation 11 with a higher R7 value, thereby reducing VINJ_SW. Use Equation 14 to calculate COUT capacitance needed. For a more holistic calculation, please reference the TPS53355 calculator on

Equation 14. GUID-20210308-CA0I-2PQB-XFD7-NKLTHWB8TDHR-low.gif

The DC voltage at the VFB pin can be calculated by Equation 15:

Equation 15. GUID-98343F2E-592E-4CE9-980C-988791C548B7-low.gif

And the resistor divider value can be determined by Equation 16:

Equation 16. GUID-5C9FA712-F41B-43F4-A542-9F4FA1057C81-low.gif