SNVSAZ4A February   2021  – March 2021 TPS541620

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Internally Compensated Advanced-Current-Mode Control
      2. 7.3.2  Enable and UVLO
      3. 7.3.3  Internal LDO
      4. 7.3.4  Pre-biased Output Start-up
      5. 7.3.5  Current Sharing
      6. 7.3.6  Frequency Selection and Minimum On-Time and Off-Time
      7. 7.3.7  Ramp Compensation Selection
      8. 7.3.8  Soft Start
      9. 7.3.9  Remote Sense Function
      10. 7.3.10 Adjustable Output Voltage
      11. 7.3.11 Power Good
      12. 7.3.12 Overcurrent Protection
      13. 7.3.13 Overvoltage and Undervoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Frequency Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Dual Independent Outputs
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Output Voltage Resistors Selection
        6. 8.2.2.6  Adjustable Undervoltage Lockout
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  BP5 Capacitor Selection
        9. 8.2.2.9  PGOOD Pullup Resistor
        10. 8.2.2.10 Current Limit
        11. 8.2.2.11 Soft-Start Time Selection
        12. 8.2.2.12 MODE1 and MODE2 Pins
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application - 2-Phase Operation
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
          1. 8.2.4.2.1  Switching Frequency
          2. 8.2.4.2.2  Output Inductor Selection
          3. 8.2.4.2.3  Output Capacitor
          4. 8.2.4.2.4  Input Capacitor
          5. 8.2.4.2.5  Output Voltage Resistors Selection
          6. 8.2.4.2.6  Adjustable Undervoltage Lockout
          7. 8.2.4.2.7  Bootstrap Capacitor Selection
          8. 8.2.4.2.8  BP5 Capacitor Selection
          9. 8.2.4.2.9  PGOOD Pullup Resistor
          10. 8.2.4.2.10 Current Limit
          11. 8.2.4.2.11 Soft-Start Time Selection
          12. 8.2.4.2.12 MODE1 Pin
        3. 8.2.4.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Input Capacitor

It is required to have input decoupling ceramic capacitors type X5R, X7R, or similar from both the PVIN1 and PVIN2 pins to PGND to bypass the power-stage and be placed as close as possible. A total of at least 10 µF of capacitance is required. Some applications can require a bulk capacitance. At least 1 µF of bypass capacitance is recommended near both VIN pins to minimize the input voltage ripple. A 0.1-µF to 1-µF capacitor must be placed by both PVIN1 and PVIN2 pins 8 and 12 to provide high frequency bypass to reduce the high frequency overshoot and undershoot on the following pins:

  • PVIN1
  • SW1
  • PVIN2
  • SW2
The voltage rating of the input capacitor must be greater than the maximum input voltage. In addition to this, more bulk capacitance can be needed on the input depending on the application to minimize variations on the input voltage during transient conditions. The input capacitance required to meet a specific input ripple target can be calculated with Equation 36. A recommended target input voltage ripple is 5% the minimum input voltage, which is 350 mV in this example. The calculated input capacitance is 2.1 µF and 4.3 µF. Use the larger of the two values and distribute evenly between PVIN1 and PVIN2. Since the values are less than 10 μF, 2 × 10 μF are used. This example meets these two requirements with 4 × 10-µF ceramic capacitors and 2 × 100-µF bulk capacitance. The capacitor must also have a ripple current rating greater than the maximum RMS input current. The RMS input current can be calculated using Equation 37 and Equation 19.

For this example design, a ceramic capacitor with at least a 16-V voltage rating is required to support the maximum input voltage. Two 10-µF, 0805, X7S, 25-V and two 0.1-μF, 0402, X7R 50-V capacitors in parallel have been selected to be placed on both sides of the IC near both PVIN pins to PGND pins. Based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 5.4 µF at the nominal input voltage of 12 V. A 100-µF bulk capacitance is also used to bypass long leads when connected a lab bench top power supply.

The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be calculated using Equation 37. The maximum input ripple occurs when operating nearest to 50% duty cycle. Using the nominal design example values of IOUT1 = 6 A, fSW = 1000 kHz, VOUT1 the input voltage ripple with the 12-V nominal input is 350 mV, and the RMS input ripple current with the 7-V minimum input is 2.106 A. Similarly, for VOUT2, the input RMS current is 3.01 A.

For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current, the selection process in the How To Select Input Capacitors For A Buck Converter technical brief is recommended.

Equation 36. GUID-20200915-CA0I-HVLW-NRBL-CGNDPSDLCZSR-low.gif

Equation 37. GUID-20200915-CA0I-7KWH-NXCT-M2XK1RGT5WXQ-low.gif
Equation 19. GUID-20200915-CA0I-QDGW-ZMSL-N4WNTCFGXZVS-low.gif