SNVSAZ4A February   2021  – March 2021 TPS541620

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency, Internally Compensated Advanced-Current-Mode Control
      2. 7.3.2  Enable and UVLO
      3. 7.3.3  Internal LDO
      4. 7.3.4  Pre-biased Output Start-up
      5. 7.3.5  Current Sharing
      6. 7.3.6  Frequency Selection and Minimum On-Time and Off-Time
      7. 7.3.7  Ramp Compensation Selection
      8. 7.3.8  Soft Start
      9. 7.3.9  Remote Sense Function
      10. 7.3.10 Adjustable Output Voltage
      11. 7.3.11 Power Good
      12. 7.3.12 Overcurrent Protection
      13. 7.3.13 Overvoltage and Undervoltage Protection
      14. 7.3.14 Overtemperature Protection
      15. 7.3.15 Frequency Synchronization
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application - Dual Independent Outputs
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Inductor Selection
        3. 8.2.2.3  Output Capacitor
        4. 8.2.2.4  Input Capacitor
        5. 8.2.2.5  Output Voltage Resistors Selection
        6. 8.2.2.6  Adjustable Undervoltage Lockout
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  BP5 Capacitor Selection
        9. 8.2.2.9  PGOOD Pullup Resistor
        10. 8.2.2.10 Current Limit
        11. 8.2.2.11 Soft-Start Time Selection
        12. 8.2.2.12 MODE1 and MODE2 Pins
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application - 2-Phase Operation
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
          1. 8.2.4.2.1  Switching Frequency
          2. 8.2.4.2.2  Output Inductor Selection
          3. 8.2.4.2.3  Output Capacitor
          4. 8.2.4.2.4  Input Capacitor
          5. 8.2.4.2.5  Output Voltage Resistors Selection
          6. 8.2.4.2.6  Adjustable Undervoltage Lockout
          7. 8.2.4.2.7  Bootstrap Capacitor Selection
          8. 8.2.4.2.8  BP5 Capacitor Selection
          9. 8.2.4.2.9  PGOOD Pullup Resistor
          10. 8.2.4.2.10 Current Limit
          11. 8.2.4.2.11 Soft-Start Time Selection
          12. 8.2.4.2.12 MODE1 Pin
        3. 8.2.4.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating junction temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MOSFET RDS(ON)
RDS(on)HS High-side FET on resistance VBST - VSW = 5 V, TJ = 25°C 24 mΩ
RDS(on)LS Low-side FET on resistance BP5 = 5 V, TJ = 25°C 10 mΩ
tDEAD(LtoH) Power stage driver dead-time from Low-side off to high-side on(1) PVIN ≥ 12 V, TJ = 25°C, ILoad = 3 A   5 ns
tDEAD(HtoL) Power stage driver dead-time from High-side off to low-side on(1) PVIN ≥ 12 V, TJ = 25°C, ILoad = 3 A  5 ns
RSW_disch SW discharge FET 32 Ω
INPUT SUPPLY and CURRENT
VPVIN1, VPVIN2 Power stage voltage 4.5 15 V
IVINSTBY PVIN bias current TJ = 25°C, EN = 5 V, non-switching 4 mA
IVINSTBY PVIN standby current  TJ = 25°C, EN1 = EN2 = 0 V 270 µA
UNDERVOLTAGE LOCKOUT
VPVIN_UVLO PVIN UVLO rising threshold VIN slew rate 1 V/1 ms 3.5 3.7 3.9 V
VPVIN_UVLO_HYS PVIN UVLO hysteresis 200 mV
VBP5 BP5 regulation voltage IOUT = 70 mA, PVIN ≥ 6 V 4.8 5 5.2 V
VBP5_UVLO_RI BP5 UVLO rising voltage 3 V
VBP5_UVLO_FA BP5 UVLO falling voltage 2.7 V
VBP5_UVLO_HYS BP5 UVLO hysteresis 300 mV
VDROPOUT LDO dropout voltage PVIN = 4.5 V, ILOAD = 70 mA 550 mV
INTERNAL REFERENCE VOLTAGE
Feedback Voltage Feedback voltage TJ = 25°C 500 mV
Feedback accuracy Feedback accuracy(1) TJ = –40°C to 125°C –1% 1%
REMOTE SENSE AMPLIFIER
fUGBW Unity gain bandwidth(1) 12 MHz
A0 Open loop gain(1) 75 dB
SR Slew rate(1) 4.7 V/µs
VICM Input range(1) –0.2 0.6 V
VOFFSET Input offset voltage(1) –1.5 1.5 mV
EN1 AND EN2 LOGIC THRESHOLD
VEN_TO_SW Enable to start switching PVIN > 4.5 V, toggle EN 0.3 ms
VEN_ON_TH EN rising threshold 1.2 1.3 V
VEN_OFF_TH EN falling threshold 1 1.1 V
VENHYS EN hysteresis 100 mV
IEN_pullup EN pullup current, EN floating PVIN = 12 V 1.4 µA
INTERNAL BOOTSTRAP SWITCH
VF BOOTSTRAP voltage drop Iboot = 10 mA 200 mV
VBOOT_UVLO BOOT UVLO 2.3 V
SWITCHING FREQUENCY
FSW FSW1 PVIN = 12 V, VOUT = 1.2 V 450 500 550 kHz
FSW2 PVIN = 12 V, VOUT = 1.2 V 900 1000 1100 kHz
FSW3 PVIN = 12 V, VOUT = 1.2 V 1350 1500 1650 kHz
FSW4 PVIN = 12 V, VOUT = 1.2 V 1800 2000 2200 kHz
ton_min SW1, SW2 minimum controllable on-time 40 50 ns
toff_min SW1, SW2 minimum controllable off time 150 200 ns
SYNCHRONIZATION
VIH(SYNC) High-level input 2 V
VIL(SYNC) Low-level input 0.6 V
DSYNC Input duty cycle 20% 80%
FSYNC to SW Sync to SW variation, % from sync to SW(1) –20% +20%
VCLKOHigh CLKO high-level output Io = 20 μA, Cload = 20 pF 2.2 V
VCLKOLow CLKO low-level output Io = 20 μA, Cload = 20 pF 0.4 V
tPSW(CLKO) Pulsewidth output Cload = 20 pF 80 ns
PRIMARY PHASE SHIFT
tSW12SW2 Phase delay from SW1 to SW2 180 °
tSYNC2SW1(P) Phase primary SYNC IN to SW1 delay in 2-phase 216 ns
SECONDARY PHASE SHIFT
tSYNC2SW1(S) Phase delay from SYNC IN to SW1 90 °
tSYNC2SW1(S) Phase delay from SYNC IN to SW2 270 °
HIGH SIDE CURRENT DETECTION
IHSOC High-side current limit, peak inductor current 12 VIN, 1 VOUT, 1 MHz 8.0 9.5 11.5 A
LOW SIDE CURRENT DETECTION
ILSOC Low-side current limit, valley inductor current 12 VIN, 1 VOUT, 1 MHz 6.2 6.8 9.0 A
ILSNOC Low-side negative current limit, valley inductor current 12 VIN, 1 VOUT, 1 MHz -4.2 -3.5 -2.8 A
Low Side Zero Cross Low-side zero cross 250 mA
tENTER_HICCUP OCP hiccup entry time 16 cycles
tHICDLY Hiccup delay time Tss = 1 ms 7 ms
OV / UV PROTECTION
VOVP Overvoltage threshold 120%
tOVPDLY OVP response time(1) 10 µs
VUVP Undervoltage threshold 80%
tUVPDLY UVP response time(1) 16 cycles
THERMAL SHUTDOWN
TSDN Built-in thermal shutdown threshold(1) 165 °C
TSDN_HYS Built-in thermal shutdown
hysteresis(1) 		20 °C
INTERNAL SOFT START
tSS_single-output Soft-start time (from switching to PGOOD high) Without CSS 1 ms
tSS_dual-output Soft-start time (from switching to PGOOD high) Fixed 1 ms
EXTERNAL SOFT START
IC_tSS CSS charge current Tss <= 50 ms, Css < 0.3 μF 2 µA
RSS Soft-start discharge FET 600 Ω
CURRENT SHARE ACCURACY
ISHARE(acc) Output current sharing accuracy, defined as the ratio of the current difference between channels to total current(sensing error only)(1) Load ≥ 0.5 × 6 A   15%
ISHARE(acc) Output current sharing accuracy, defined as the ratio of the current difference between channels to total current(sensing error only)(1) Load < 0.5 × 6 A   1 A
VISHARE_L Fault voltage falling 200 mV
VISHARE_L Fault voltage rising 300 mV
POWER GOOD COMPARATOR
VPG(thresh) Power good threshold (%VFB) FB falling, PG high to low 87% 90% 93%
VPG(thresh) Power good threshold (%VFB) FB rising, PG low to high 90% 93% 96%
VPG(thresh) Power good threshold (%VFB) FB rising, PG high to low 107% 110% 113%
VPG(thresh) Power good threshold (%VFB) FB falling, PG low to high 104% 107% 110%
IPGD_lkg PGOOD1, PGOOD2 leakage current V(PGOOD1) = V(PGOOD2) = 5.5 V 1 µA
tPGDLY Delay for PGOOD low to high 50 µs
tPGDLY Delay for PGOOD high to low 10 µs
VPGDLOW PGOOD output low voltage VIN = 4 V, VOUT = 0 V, IPGOOD = 6 mA 0.4 V
VMINVIN_OUTPUT Minimum PVIN for asserted output VPGOOD ≤ 0.4V 1.5 V
(1) Specified by design. Not production tested.