SLVSD26A April 2016 – January 2017 TPS54202
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS54202 are typically used as a step down converter, which convert an input voltage from 8 V - 28 V to fixed output voltage 5 V.
For this design example, use the parameters in Table 1.
PARAMETER | VALUE |
---|---|
Input voltage range | 8 V to 28 V |
Output voltage | 5 V |
Output current | 2 A |
Transient response, 1.5 A load step | ΔV_{OUT} = ±5 % |
Input ripple voltage | 400 mV |
Output voltage ripple | 30 mVpp |
Switching frequency | 500 kHz |
The device requires an input decoupling capacitor and a bulk capacitor is needed depending on the application. A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An additional 0.1 µF capacitor (C2) from VIN to GND is optional to provide additional high frequency filtering. The capacitor voltage rating needs to be greater than the maximum input voltage.
Use Equation 4 to calculate the input ripple voltage (ΔV_{IN}).
where
The maximum RMS (root mean square) ripple current must also be checked. For worst case conditions, use Equation 5 to calculate I_{CIN(RMS)}.
The actual input-voltage ripple is greatly affected by parasitic associated with the layout and the output impedance of the voltage source. Design Requirements show the actual input voltage ripple for this circuit which is larger than the calculated value. This measured value is still below the specified input limit of 400 mV. The maximum voltage across the input capacitors is VIN (MAX) + ΔVIN/2. The selected bypass capacitor is rated for 35 V and the ripple current capacity is greater than 2 A. Both values provide ample margin. The maximum ratings for voltage and current must not be exceeded under any circumstance.
A 0.1 µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. It is recommended to use a ceramic capacitor.
The output voltage of the TPS54202 device is externally adjustable using a resistor divider network. In the application circuit of Figure 16, this divider network is comprised of R2 and R3. Use Equation 6 and Equation 7 to calculate the relationship of the output voltage to the resistor divider.
Select a value of R2 to be approximately 100 kΩ. Slightly increasing or decreasing R3 can result in closer output voltage matching when using standard value resistors. In this design, R2 = 100 kΩ and R3 = 13.3 kΩ which results in a 5-V output voltage. The 49.9-Ω resistor, R1, is provided as a convenient location to break the control loop for stability testing.
The undervoltage lockout (UVLO) set point can be adjusted using the external-voltage divider network of R4 and R5. R4 is connected between the VIN and EN pins of the TPS54202 device. R5 is connected between the EN and GND pins. The UVLO has two thresholds, one for power up when he input voltage is rising and one for power down or brown outs when the input voltage is falling. For the example design, the minimum input voltage is 8 V, so the start-voltage threshold is set to 6.8 V with 1000-mV hysteresis. Use Equation 1 and Equation 2 to calculate the values for the upper and lower resistor values of R4 and R5.
Two components must be selected for the output filter, the output inductor (L_{O}) and C_{O}.
Use Equation 8 to calculate the minimum value of the output inductor (L_{MIN}).
Where:
K_{IND} is a coefficient that represents the amount of inductor ripple current relative to the maximum output current.
In general, the value of K_{IND} is at the discretion of the designer; however, the following guidelines may be used. For designs using low-ESR output capacitors, such as ceramics, a value as high as K_{IND} = 0.3 can be used. When using higher ESR output capacitors, K_{IND} = 0.2 yields better results.
For this design example, use K_{IND} = 0.3. The minimum inductor value is calculated as 13.7 μH. For this design, a close standard value of 15 μH was selected for L_{MIN}.
For the output filter inductor, the RMS current and saturation current ratings must not be exceeded. Use Equation 9 to calculate the RMS inductor current (I_{L(RMS)}).
Use Equation 10 to calculate the peak inductor current (I_{L(PK)}).
Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow so long as the other design requirements are met. Larger value inductors have lower AC current and result in lower output voltage ripple. Smaller inductor values increase AC current and output voltage ripple.
Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for the regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition from no load to full load. The regulator usually requires two or more clock cycles for the control loop to notice the change in load current and output voltage and to adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of drop in the output voltage. Use Equation 11 to calculate the minimum required output capacitance.
where
For this example, the transient load response is specified as a 5% change in the output voltage, V_{OUT}, for a load step of 1.5 A. For this example, ΔI_{OUT} = 1.5 A and ΔV_{OUT} = 0.05 × 5 = 0.25 V. Using these values results in a minimum capacitance of 24 μF. This value does not consider the ESR of the output capacitor in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
Equation 12 calculates the minimum output capacitance required to meet the output voltage ripple specification. In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 12 yields 4.56 μF.
where
Use Equation 13 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple specification. Equation 13 indicates the ESR should be less than 54.8 mΩ. In this case, the ESR of the ceramic capacitor is much smaller than 54.8 mΩ.
The output capacitor can affect the crossover frequency ƒ_{o}. Considering to the loop stability and effect of the internal parasitic parameters, choose the crossover frequency less than 40 kHz without considering the feed forward capacitor. A simple estimation for the crossover frequency without feed forward capacitor C6 is shown in Equation 14, assuming C_{OUT} has small ESR.
Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases this minimum value. For this example, two 22-uF 25-V, X7R ceramic capacitors are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS value of the maximum ripple current. Use Equation 15 to calculate the RMS ripple current that the output capacitor must support. For this application, Equation 15 yields 79 mA for each capacitor.
The TPS54202 is internally compensated and the internal compensation network is composed of two capacitors and one resister shown on the block diagram. Depending on the V_{OUT}, if the output capacitor C_{OUT} is dominated by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feedforward capacitor C6 can be added in parallel with R2. C6 is chosen such that phase margin is boosted at the crossover frequency.
Equation 16 for C6 was tested:
For this design, C6 = 75 pF. C6 is not needed when C_{OUT} has high ESR, and C6 calculated from Equation 16 should be reduced with medium ESR. Table 2 can be used as a starting point.
V_{OUT} (V) | L (µH) ^{(1)} | C_{OUT}(µF) | R2 (kΩ) | R3 (kΩ) | C6 (pF) |
---|---|---|---|---|---|
1.8 | 5.6 | 66 | 100 | 49.9 | 47 |
2.5 | 8.2 | 44 | 100 | 31.6 | 33 |
3.3 | 10 | 44 | 100 | 22.1 | 56 |
5 | 15 | 44 | 100 | 13.3 | 75 |
12 | 22 | 44 | 100 | 5.23 | 100 |
I_{OUT} = 0 A |
I_{OUT} = 100 mA |
0.1 to 1 A |
I_{OUT} = 2 A |
I_{OUT} = 10 mA |
I_{OUT} = 2 A |
0.5 to 1.5 A |