SLVS839F July 2008 – October 2014 TPS54331
PRODUCTION DATA.
The external compensation used with the TPS54331 device allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.
A Type II compensation scheme is recommended for the TPS54331 device. The compensation components are selected to set the desired closed-loop crossover frequency and phase margin for output filter components. The Type II compensation has the following characteristics: a DC gain component, a low frequency pole, and a mid frequency zero-pole pair.
Use Equation 16 to calculate the DC gain.
where
Use Equation 17 to calculate the low-frequency pole.
Use Equation 18 to calculate the mid-frequency zero.
Use Equation 19 to calculate the mid-frequency pole.
The first step is to select the closed-loop crossover frequency. In general, the closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency. However, for the TPS54331 device, not exceeding 25 kHz for the maximum closed-loop crossover frequency is recommended. The second step is to calculate the required gain and phase boost of the crossover network. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 20.
Use Equation 21 to calculate the phase loss.
where
The measured overall loop-response for the circuit is given in Figure 16. The actual closed-loop crossover frequency is higher than intended at about 25 kHz which is primarily because variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall, the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of line and load variability.
Now that the phase loss is known, the required amount of phase boost to meet the phase margin requirement can be determined. Use Equation 22 to calculate the required phase boost.
where
A zero-pole pair of the compensation network will be placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be calculated with Equation 23. Use Equation 24 and Equation 25 to calculate the resultant zero and pole frequencies.
The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Because of the relationships established by the pole and zero relationships, use Equation 26 to calculate the value of R_{Z}.
where
With the value of R_{Z} known, use Equation 27 and Equation 28 to calculate the values of C_{Z} and C_{P}.
For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied which occurs in a DC-DC converter. The actual output capacitance may be as low as 54 μF. The combined ESR is approximately 0.001 Ω.
Using Equation 20 and Equation 21, the output stage gain and phase loss are equivalent as:
Gain = –2.26 dB
PL = –83.52 degrees
For 70 degrees of phase margin, Equation 22 requires 63.52 degrees of phase boost.
Use Equation 23, Equation 24, and Equation 25 to calculate the zero and pole frequencies of the following values:
F_{Z1} = 5883 Hz
F_{P1} = 106200 Hz
Use Equation 26, Equation 27, and Equation 28 to calculate the values of R_{Z}, C_{Z}, and C_{P}.
Referring to Figure 10 and using standard values for R3, C6, and C7, the calculated values are as follows:
R3 = 29.4 kΩ
C6 = 1000 pF
C7 = 47 pF