SLVS839F July   2008  – October 2014 TPS54331


  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
    1.     TPS54331 (D Package) Efficiency
  5. Revision History
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency PWM Control
      2. 8.3.2  Voltage Reference (Vref)
      3. 8.3.3  Bootstrap Voltage (BOOT)
      4. 8.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 8.3.5  Programmable Slow Start Using SS Pin
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Slope Compensation
      8. 8.3.8  Current-Mode Compensation Design
      9. 8.3.9  Overcurrent Protection and Frequency Shift
      10. 8.3.10 Overvoltage Transient Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Eco-mode™
      2. 8.4.2 Operation With VIN < 3.5 V
      3. 8.4.3 Operation With EN Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Custom Design with WEBENCH Tools
        2.  Switching Frequency
        3.  Output Voltage Set Point
        4.  Input Capacitors
        5.  Output Filter Components
          1. Inductor Selection
        6.  Capacitor Selection
        7.  Compensation Components
        8.  Bootstrap Capacitor
        9.  Catch Diode
        10. Output Voltage Limitations
        11. Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Electromagnetic Interference (EMI) Considerations
  12. 12Device and Documentation Support
    1. 12.1 Custom Design with WEBENCH Tools
    2. 12.2 Device Support
      1. 12.2.1 Development Support
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Compensation Components

The external compensation used with the TPS54331 device allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.

A Type II compensation scheme is recommended for the TPS54331 device. The compensation components are selected to set the desired closed-loop crossover frequency and phase margin for output filter components. The Type II compensation has the following characteristics: a DC gain component, a low frequency pole, and a mid frequency zero-pole pair.

Use Equation 16 to calculate the DC gain.

Equation 16. TPS54331 new_eq12_lvs839.gif


  • Vggm = 800
  • VREF = 0.8 V

Use Equation 17 to calculate the low-frequency pole.

Equation 17. TPS54331 new_eq13_lvs839.gif

Use Equation 18 to calculate the mid-frequency zero.

Equation 18. TPS54331 new_eq14_lvs839.gif

Use Equation 19 to calculate the mid-frequency pole.

Equation 19. TPS54331 new_eq15_lvs839.gif

The first step is to select the closed-loop crossover frequency. In general, the closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency. However, for the TPS54331 device, not exceeding 25 kHz for the maximum closed-loop crossover frequency is recommended. The second step is to calculate the required gain and phase boost of the crossover network. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 20.

Equation 20. TPS54331 new_eq16_lvs839.gif


  • RSENSE = 1 Ω / 12
  • FCO = Closed-loop crossover frequency
  • CO = Output capacitance

Use Equation 21 to calculate the phase loss.

Equation 21. TPS54331 new_eq17_lvs839.gif


  • RESR = Equivalent series resistance of the output capacitor
  • RO = VO / IO

The measured overall loop-response for the circuit is given in Figure 16. The actual closed-loop crossover frequency is higher than intended at about 25 kHz which is primarily because variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall, the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of line and load variability.

Now that the phase loss is known, the required amount of phase boost to meet the phase margin requirement can be determined. Use Equation 22 to calculate the required phase boost.

Equation 22. TPS54331 new_eq_lvs839.gif


  • PM = the desired phase margin

A zero-pole pair of the compensation network will be placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be calculated with Equation 23. Use Equation 24 and Equation 25 to calculate the resultant zero and pole frequencies.

Equation 23. TPS54331 q18_k_lvs839.gif
Equation 24. TPS54331 q19_fz1fco_lvs839.gif
Equation 25. TPS54331 q20_fp1fco_lvs839.gif

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Because of the relationships established by the pole and zero relationships, use Equation 26 to calculate the value of RZ.

Equation 26. TPS54331 q21_rz_lvs839.gif


  • VO = Output voltage
  • CO = Output capacitance
  • FCO = Desired crossover frequency
  • ROA = 8 MΩ
  • GMCOMP = 12 A/V
  • Vggm = 800
  • VREF = 0.8 V

With the value of RZ known, use Equation 27 and Equation 28 to calculate the values of CZ and CP.

Equation 27. TPS54331 q22_cz_lvs839.gif
Equation 28. TPS54331 q23_cp_lvs839.gif

For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied which occurs in a DC-DC converter. The actual output capacitance may be as low as 54 μF. The combined ESR is approximately 0.001 Ω.

Using Equation 20 and Equation 21, the output stage gain and phase loss are equivalent as:

Gain = –2.26 dB

PL = –83.52 degrees

For 70 degrees of phase margin, Equation 22 requires 63.52 degrees of phase boost.

Use Equation 23, Equation 24, and Equation 25 to calculate the zero and pole frequencies of the following values:

FZ1 = 5883 Hz

FP1 = 106200 Hz

Use Equation 26, Equation 27, and Equation 28 to calculate the values of RZ, CZ, and CP.

Equation 29. TPS54331 q_rz_solv_lvs839.gif
Equation 30. TPS54331 q_cz_solv_lvs839.gif
Equation 31. TPS54331 q_cp_solv_lvs839.gif

Referring to Figure 10 and using standard values for R3, C6, and C7, the calculated values are as follows:

R3 = 29.4 kΩ

C6 = 1000 pF

C7 = 47 pF