SLVS839F July   2008  – October 2014 TPS54331

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
    1.     TPS54331 (D Package) Efficiency
  5. Revision History
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed-Frequency PWM Control
      2. 8.3.2  Voltage Reference (Vref)
      3. 8.3.3  Bootstrap Voltage (BOOT)
      4. 8.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 8.3.5  Programmable Slow Start Using SS Pin
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Slope Compensation
      8. 8.3.8  Current-Mode Compensation Design
      9. 8.3.9  Overcurrent Protection and Frequency Shift
      10. 8.3.10 Overvoltage Transient Protection
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Eco-mode™
      2. 8.4.2 Operation With VIN < 3.5 V
      3. 8.4.3 Operation With EN Control
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design with WEBENCH Tools
        2. 9.2.2.2  Switching Frequency
        3. 9.2.2.3  Output Voltage Set Point
        4. 9.2.2.4  Input Capacitors
        5. 9.2.2.5  Output Filter Components
          1. 9.2.2.5.1 Inductor Selection
        6. 9.2.2.6  Capacitor Selection
        7. 9.2.2.7  Compensation Components
        8. 9.2.2.8  Bootstrap Capacitor
        9. 9.2.2.9  Catch Diode
        10. 9.2.2.10 Output Voltage Limitations
        11. 9.2.2.11 Power Dissipation Estimate
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Electromagnetic Interference (EMI) Considerations
  12. 12Device and Documentation Support
    1. 12.1 Custom Design with WEBENCH Tools
    2. 12.2 Device Support
      1. 12.2.1 Development Support
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Voltage Limitations

Because of the internal design of the TPS54331 device, any given input voltage has both upper and lower output voltage limits. The upper limit of the output-voltage set point is constrained by the maximum duty cycle of 91% and is calculated with Equation 32.

Equation 32. TPS54331 q24_vomax_lvs839.gif

where

  • VIN(MIN) = Minimum input voltage
  • IO(MAX) = Maximum load current
  • VD = Catch diode forward voltage
  • RL = Output inductor series resistance

The equation assumes the maximum ON resistance for the internal high-side FET.

The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns. Use Equation 33 to calculate the approximate minimum output voltage for a given input voltage and minimum load current.

Equation 33. TPS54331 q32_vomin_lvs839.gif

where

  • VIN(MAX) = Maximum input voltage
  • IO(MIN) = Minimum load current
  • VD = Catch diode forward voltage
  • RL = Output inductor series resistance

The nominal on-resistance for the high-side FET in Equation 33 is assumed. Equation 33 accounts for the worst case variation of operating-frequency set point. Any design operating near the operational limits of the device should be carefully checked to ensure proper functionality.