SLVS839F July 2008 – October 2014 TPS54331
Because of the internal design of the TPS54331 device, any given input voltage has both upper and lower output voltage limits. The upper limit of the output-voltage set point is constrained by the maximum duty cycle of 91% and is calculated with Equation 32.
The equation assumes the maximum ON resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which can be as high as 130 ns. Use Equation 33 to calculate the approximate minimum output voltage for a given input voltage and minimum load current.
The nominal on-resistance for the high-side FET in Equation 33 is assumed. Equation 33 accounts for the worst case variation of operating-frequency set point. Any design operating near the operational limits of the device should be carefully checked to ensure proper functionality.