SLVS875C January   2009  – November 2014 TPS54332


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics: Characterization Curves
    8. 6.8 Typical Characteristics: Supplemental Application Curves
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Voltage Reference (Vref)
      3. 7.3.3  Bootstrap Voltage (BOOT)
      4. 7.3.4  Enable and Adjustable Input Undervoltage Lockout (VIN UVLO)
      5. 7.3.5  Programmable Slow-Start Using SS Pin
      6. 7.3.6  Error Amplifier
      7. 7.3.7  Slope Compensation
      8. 7.3.8  Current Mode Compensation Design
      9. 7.3.9  Overcurrent Protection and Frequency Shift
      10. 7.3.10 Overvoltage Transient Protection
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Operation With VIN < 3.5 V
      2. 7.4.2 Operation With EN Control
      3. 7.4.3 Eco-Mode
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Switching Frequency
        2.  Output Voltage Set Point
        3.  Input Capacitors
        4.  Output Filter Components
        5.  Inductor Selection
        6.  Capacitor Selection
        7.  Compensation Components
        8.  Bootstrap Capacitor
        9.  Catch Diode
        10. Output Voltage Limitations
        11. Power Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Estimated Circuit Area
    4. 10.4 Electromagnetic Interference (EMI) Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Compensation Components

The external compensation used with the TPS54332 allows for a wide range of output filter configurations. A large range of capacitor values and types of dielectric are supported. The design example uses ceramic X5R dielectric output capacitors, but other types are supported.

A Type II compensation scheme is recommended for the TPS54332. The compensation components are chosen to set the desired closed-loop crossover frequency and phase margin for output filter components. The type II compensation has the following characteristics; a DC gain component, a low-frequency pole, and a mid-frequency zero or pole pair.

The DC gain is determined by Equation 17.

Equation 17. TPS54332 new_eq12_lvs839.gif


Vggm = 800
VREF = 0.8 V

The low-frequency pole is determined by Equation 18.

Equation 18. TPS54332 q_fpo_lvs875.gif

ROA = 8.696 MΩ.

The mid-frequency zero is determined by Equation 19.

Equation 19. TPS54332 new_eq14_lvs839.gif

And, the mid-frequency pole is given by Equation 20.

Equation 20. TPS54332 new_eq15_lvs839.gif

The first step is to choose the closed-loop crossover frequency. The closed-loop crossover frequency should be less than 1/8 of the minimum operating frequency, but for the TPS54332 it is recommended that the maximum closed-loop crossover frequency be not greater than 75 kHz. Next, the required gain and phase boost of the crossover network needs to be calculated. By definition, the gain of the compensation network must be the inverse of the gain of the modulator and output filter. For this design example, where the ESR zero is much higher than the closed-loop crossover frequency, the gain of the modulator and output filter can be approximated by Equation 21.

Equation 21. TPS54332 new_eq16_lvs839.gif


RSENSE = 1 Ω / 12

FCO = Closed-loop crossover frequency

CO = Output capacitance

The phase loss is given by Equation 22.

Equation 22. TPS54332 q_pl_tan_lvs875.gif


RESR = Equivalent series resistance of the output capacitor


The measured overall loop response for the circuit is given in Figure 20. Note that the actual closed-loop crossover frequency is higher than intended at about 25 kHz. This is primarily due to variation in the actual values of the output filter components and tolerance variation of the internal feed-forward gain circuitry. Overall the design has greater than 60 degrees of phase margin and will be completely stable over all combinations of line and load variability.

Now that the phase loss is known the required amount of phase boost to meet the phase margin requirement can be determined. The required phase boost is given by Equation 23.

Equation 23. TPS54332 new_eq_lvs839.gif

Where PM = the desired phase margin.

A zero / pole pair of the compensation network will be placed symmetrically around the intended closed-loop frequency to provide maximum phase boost at the crossover point. The amount of separation can be determined by Equation 24 and the resultant zero and pole frequencies are given by Equation 25 and Equation 26.

Equation 24. TPS54332 q18_k_lvs839.gif
Equation 25. TPS54332 q19_fz1fco_lvs839.gif
Equation 26. TPS54332 q20_fp1fco_lvs839.gif

The low-frequency pole is set so that the gain at the crossover frequency is equal to the inverse of the gain of the modulator and output filter. Due to the relationships established by the pole and zero relationships, the value of RZ can be derived directly by Equation 27 .

Equation 27. TPS54332 q21_rz_lvs839.gif


VO = Output voltage

CO = Output capacitance

FCO = Desired crossover frequency

ROA = 8.696 MΩ


Vggm = 800

VREF = 0.8 V

With RZ known, CZ and CP can be calculated using Equation 28 and Equation 29.

Equation 28. TPS54332 q22_cz_lvs839.gif
Equation 29. TPS54332 q23_cp_lvs839.gif

For this design, the two 47-μF output capacitors are used. For ceramic capacitors, the actual output capacitance is less than the rated value when the capacitors have a DC bias voltage applied. This is the case in a dc/dc converter. The actual output capacitance may be as low as 54 μF. The combined ESR is approximately .001 Ω.

Using Equation 21 and Equation 22, the output stage gain and phase loss are equivalent as:

Gain = –6.94 dB


PL - –93.94 degrees

For 70 degrees of phase margin, Equation 23 requires 63.64 degrees of phase boost.

Equation 24, Equation 25, and Equation 26 are used to find the zero and pole frequencies of:

FZ1 = 11.57 kHz


FP1 = 216 kHz

RZ, CZ, and CP are calculated using Equation 27, Equation 28, and Equation 29.

Equation 30. TPS54332 q_rz_solv_lvs875.gif
Equation 31. TPS54332 q_cz_solv_lvs875.gif
Equation 32. TPS54332 q_cp_solv_lvs875.gif

Using standard values for R3, C6, and C7 in the application schematic of Figure 12.

R3 = 75 kΩ

C6 = 180 pF

C7 = 10 pF