SLVSAF1E October 2010 – May 2019 TPS54388-Q1
The industry uses several techniques to compensate dc-dc regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54388-Q1 device. As a result of ignoring the slope compensation, the actual crossover frequency is usually lower than the crossover frequency used in the calculations.
To get started, calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using Equation 36 and Equation 37. For C(OUT), derating the capacitor is not necessary, as the 1.8-V output is a small percentage of the 10-V capacitor rating. If the output is a high percentage of the capacitor rating, use the manufacturer information for the capacitor to derate the capacitor value. Use Equation 38 and Equation 39 to estimate a starting point for the crossover frequency, f(c). For the example design, f(p,mod) is 6.03 kHz and f(z,mod) is 1210 kHz. Equation 38 is the geometric mean of the modulator pole and the ESR zero, and Equation 39 is the mean of the modulator pole and the switching frequency. Equation 38 yields 85.3 kHz and Equation 39 gives 54.9 kHz. Use the lower value of Equation 38 or Equation 39 as the approximate crossover frequency. For this example, f(c) is 56 kHz. Next, calculate the values of the compensation components. Use a resistor in series with a capacitor to create a compensating zero. A capacitor in parallel with these two components forms the compensating pole (if needed).
The compensation design takes the following steps:
From the procedures above, the compensation network includes a 7.68-kΩ resistor and a 3300-pF capacitor.