SLVSAF1E October   2010  – May 2019 TPS54388-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency Curve
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using the RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Output-Voltage and Feedback-Resistor Selection
        9. 8.2.2.9  Compensation
        10. 8.2.2.10 Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Development Support
        1. 11.2.1.1 Custom Design With WEBENCH® Tools
    3. 11.3 Documentation Support
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resource
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

TJ = –40°C to 150°C, V(VIN) = 2.95 to 6 V (unless otherwise noted)
DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
Internal undervoltage lockout threshold VIN UVLO start 2.28 2.5 V
VIN UVLO stop 2.45 2.6
Shutdown supply current V(EN) = 0 V, 25°C, 2.95 V ≤ V(VIN) ≤ 6 V 5.5 15 μA
Quiescent current, I(q) V(SENSE) = 0.9 V, V(VIN) = 5 V, 25°C, Rt = 400 kΩ 515 750 μA
ENABLE AND UVLO (EN PIN)
Enable threshold Rising 1.25 V
Falling 1.18
Input current Enable threshold + 50 mV –1.6 μA
Enable threshold – 50 mV –1.6
VOLTAGE REFERENCE (VSENSE PIN)
Voltage reference 2.95 V ≤ V(VIN) ≤ 6 V, –40°C <TJ < 150°C 0.79 0.8 0.811 V
MOSFET
High-side switch resistance V(BOOT-PH) = 5 V 12 30 mΩ
V(BOOT-PH) = 2.95 V 16 30
Low-side switch resistance V(VIN) = 5 V 13 30 mΩ
V(VIN) = 2.95 V 17 30
ERROR AMPLIFIER
Input current 2 nA
Error-amplifier transconductance (gm) –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V 245 μS
Error-amplifier transconductance (gm) during slow start –2 μA < I(COMP) < 2 μA, V(COMP) = 1 V,
V(VSENSE) = 0.4 V
79 μS
Error amplifier source and sink V(COMP) = 1 V, 100-mV overdrive ±20 μA
COMP to high-side FET current gm 25 S
CURRENT LIMIT
Current limit threshold 3.7 6.5 A
THERMAL SHUTDOWN
Thermal shutdown 168 °C
Hysteresis 20 °C
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequency range using RT mode 200 2000 kHz
Switching frequency Rt = 400 kΩ 400 500 600 kHz
Switching frequency range using CLK mode 300 2000 kHz
Minimum CLK pulse duration 75 ns
RT/CLK voltage Rt = 400 kΩ 0.5 V
RT/CLK high threshold 1.6 2.5 V
RT/CLK low threshold 0.4 0.6 V
Delay from RT/CLK falling edge to PH rising edge Measure at 500 kHz with RT resistor in series with device pin 90 ns
PLL lock-in time Measure at 500 kHz 45 μs
PH (PH PIN)
Minimum on-time Measured at 50% point on PH, IO = 3 A 75 ns
Measured at 50% point on PH, V(VIN) = 6 V,
IO = 0 A
120
Minimum off-time Prior to skipping off pulses, BOOT-PH = 2.95 V,
IO = 3 A
60 ns
Rise time V(VIN) = 6 V, 6 A 2.25 V/ns
Fall time V(VIN) = 6 V, 6 A 2
BOOT (BOOT PIN)
BOOT charge resistance V(VIN) = 5 V 16
BOOT-PH UVLO V(VIN) = 2.95 V 2.1 V
SLOW START AND TRACKING (SS/TR PIN)
Charge current V(SS/TR) = 0.4 V 2 μA
SS/TR to VSENSE matching V(SS/TR) = 0.4 V 50 mV
SS/TR to reference crossover 98% of normal reference voltage 1.1 V
SS/TR discharge voltage (overload) V(VSENSE) = 0 V 61 mV
SS/TR discharge current (overload) V(VSENSE) = 0 V, V(SS/TR) = 0.4 V 350 µA
SS discharge current (UVLO, EN, thermal fault) V(VIN) = 5 V, V(SS/TR) = 0.5 V 1.9 mA
POWER GOOD (PWRGD PIN)
VSENSE threshold VSENSE falling (Fault) 91 % Vref
VSENSE rising (Good) 93
VSENSE rising (Fault) 109
VSENSE falling (Good) 107
Hysteresis VSENSE falling 2 % Vref
Output-high leakage V(VSENSE) = Vref, V(PWRGD) = 5.5 V 7 nA
On-resistance 56 100
Output low I(PWRGD) = 3 mA 0.3 V
Minimum VIN for valid output V(PWRGD) < 0.5 V at 100 μA 0.65 1.6 V