SLVSAF1E October   2010  – May 2019

PRODUCTION DATA.

1. Features
2. Applications
3. Description
1.     Device Images
4. Revision History
5. Pin Configuration and Functions
6. Specifications
7. Detailed Description
1. 7.1 Overview
2. 7.2 Functional Block Diagram
3. 7.3 Feature Description
4. 7.4 Device Functional Modes
8. Application and Implementation
1. 8.1 Application Information
2. 8.2 Typical Application
1. 8.2.1 Design Requirements
2. 8.2.2 Detailed Design Procedure
3. 8.2.3 Application Curves
9. Power Supply Recommendations
10. 10Layout
11. 11Device and Documentation Support
12. 12Mechanical, Packaging, and Orderable Information

• RTE|16
• RTE|16

#### 8.2.2.5 Input Capacitor

The TPS54388-Q1 device requires a high-quality ceramic, type X5R or X7R, input decoupling capacitor with at least 4.7 μF of effective capacitance, and in some applications a bulk capacitance. The effective capacitance includes any dc bias effects. The voltage rating of the input capacitor must be greater than the maximum input voltage. The capacitor must also have a ripple-current rating greater than the maximum input-current ripple of the TPS54388-Q1 device. Calculate the input ripple current using Equation 30.

The value of a ceramic capacitor varies significantly over temperature and the amount of dc bias applied to the capacitor. Minimize the capacitance variations due to temperature by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are the usual selection for power regulator capacitors because they have a high capacitance-to-volume ratio and are fairly stable over temperature. The output-capacitor selection must also take dc bias into account. The capacitance value of a capacitor decreases as the dc bias across that capacitor increases.

This example design requires a ceramic capacitor with at least a 10-V voltage rating to support the maximum input voltage. For this example, the selection is one 10-μF 10-V and one 0.1-μF 10-V capacitor in parallel. The input capacitance value determines the input ripple voltage of the regulator. Calculate the input voltage ripple using Equation 31. Using the design example values, IO(max) = 3 A, C(IN) = 10 μF, and f(SW) = 1 MHz, yields an input voltage ripple of 76 mV and an rms input ripple current of 1.47 A.

Equation 30.
Equation 31.