SLVSAF1E October 2010 – May 2019 TPS54388-Q1
Layout is a critical portion of good power-supply design. The signal paths, which conduct fast-changing currents or voltages, can interact with stray inductance or parasitic capacitance in several ways to generate noise or degrade the power-supply performance. Take care to minimize the loop area formed by the bypass-capacitor connections and the VIN pins. See Figure 49 for a PCB layout example. Tie the GND pins and AGND pin directly to the thermal pad under the IC. Connect the thermal pad to any internal PCB ground planes using multiple vias directly under the IC. Use additional vias to connect the top-side ground area to any internal planes near the input and output capacitors. For operation at full-rated load, the top-side ground area, along with any additional internal ground planes, must provide adequate heat-dissipating area.
Locate the input bypass capacitor as close to the IC as possible. Route the PH pin to the output inductor. Because the PH connection is the switching node, locate the output inductor close to the PH pins, and minimize the area of the PCB conductor to prevent excessive capacitive coupling. Also. locate the boot capacitor close to the device. Connect the sensitive analog ground connections for the feedback voltage divider, compensation components, slow-start capacitor, and frequency-set resistor to a separate analog ground trace as shown. The RT/CLK pin is particularly sensitive to noise, so locate the Rt resistor as close as possible to the IC, and connect it with minimal lengths of trace. Place the additional external components approximately as shown. It may be possible to obtain acceptable performance with alternative PCB layouts. However, this layout, meant as a guideline, produces good results.