SLVSAF1E October   2010  – May 2019 TPS54388-Q1


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency Curve
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using the RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Custom Design With WEBENCH® Tools
        2.  Selecting the Switching Frequency
        3.  Output Inductor Selection
        4.  Output Capacitor
        5.  Input Capacitor
        6.  Slow-Start Capacitor
        7.  Bootstrap Capacitor Selection
        8.  Output-Voltage and Feedback-Resistor Selection
        9.  Compensation
        10. Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Development Support
        1. Custom Design With WEBENCH® Tools
    3. 11.3 Documentation Support
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resource
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD pins. Implementation of the sequential method uses an open-drain or open-collector output of the power-on-reset pin of another device. Figure 23 shows the sequential method. Couple the power-good to the EN pin on the TPS54388-Q1 device to enable the second power supply once the primary supply reaches regulation.

One can accomplish ratiometric start-up by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, double the pullup current source in Equation 4. Figure 25 shows the ratiometric method.

TPS54388-Q1 startup_SLVSAF1.gifFigure 23. Sequential Start-Up Sequence
TPS54388-Q1 sequential_SLVSAH5.gifFigure 24. Sequential Start-Up Using EN and PWRGD
TPS54388-Q1 rad_stup_lvs975.gifFigure 25. Schematic for Ratiometric Start-Up Sequence
TPS54388-Q1 SS_ratio_SLVSAH5.gifFigure 26. Ratiometric Start-Up With VO(1) Leading VO(2)

One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of R1 and R2 shown in Figure 27 to the output of the power supply that requires tracking, or to another voltage reference source. Using Equation 5 and Equation 6, one can calculate the tracking resistors to initiate VO(2) slightly before, after, or at the same time as VO(1). VO(1) – VO(2) is 0 V for simultaneous sequencing. Including V(ssoffset) and I(SS/TR) as variables in the equations minimizes the effect of the inherent SS/TR-to-VSENSE offset (V(ssoffset)) in the slow-start circuit and the offset created by the pullup current source (I(ss)) and tracking resistors. Because the SS/TR pin requires pulling below 60 mV before starting after an EN, UVLO, or thermal-shutdown fault, select the tracking resistors carefully to ensure the device can restart after a fault. Make sure the calculated R1 value from Equation 5 is greater than the value calculated in Equation 7 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V(ssoffset) becomes larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.1 V for a complete handoff to the internal voltage reference as shown in Figure 26.

Equation 5. TPS54388-Q1 eq05_r1_SLVSAH5.gif
Equation 6. TPS54388-Q1 eq36_r2_SLVSAH5.gif
Equation 7. TPS54388-Q1 eqD_R1_SLVSAH5.gif
TPS54388-Q1 ratiosimul_stup_SLVSAF1.gifFigure 27. Ratiometric and Simultaneous Start-Up Sequence
TPS54388-Q1 tracking_SLVSAH5.gifFigure 28. Ratiometric Start-Up Using Coupled SS/TR Pins