SLVSAF1E October 2010 – May 2019 TPS54388-Q1
One can implement many of the common power-supply sequencing methods using the SS/TR, EN, and PWRGD pins. Implementation of the sequential method uses an open-drain or open-collector output of the power-on-reset pin of another device. Figure 23 shows the sequential method. Couple the power-good to the EN pin on the TPS54388-Q1 device to enable the second power supply once the primary supply reaches regulation.
One can accomplish ratiometric start-up by connecting the SS/TR pins together. The regulator outputs ramp up and reach regulation at the same time. When calculating the slow-start time, double the pullup current source in Equation 4. Figure 25 shows the ratiometric method.
One can implement ratiometric and simultaneous power-supply sequencing by connecting the resistor network of R1 and R2 shown in Figure 27 to the output of the power supply that requires tracking, or to another voltage reference source. Using Equation 5 and Equation 6, one can calculate the tracking resistors to initiate VO(2) slightly before, after, or at the same time as VO(1). VO(1) – VO(2) is 0 V for simultaneous sequencing. Including V(ssoffset) and I(SS/TR) as variables in the equations minimizes the effect of the inherent SS/TR-to-VSENSE offset (V(ssoffset)) in the slow-start circuit and the offset created by the pullup current source (I(ss)) and tracking resistors. Because the SS/TR pin requires pulling below 60 mV before starting after an EN, UVLO, or thermal-shutdown fault, select the tracking resistors carefully to ensure the device can restart after a fault. Make sure the calculated R1 value from Equation 5 is greater than the value calculated in Equation 7 to ensure the device can recover from a fault. As the SS/TR voltage becomes more than 85% of the nominal reference voltage, V(ssoffset) becomes larger as the slow-start circuits gradually hand off the regulation reference to the internal voltage reference. The SS/TR pin voltage must be greater than 1.1 V for a complete handoff to the internal voltage reference as shown in Figure 26.