SLVSAF1E October   2010  – May 2019 TPS54388-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency Curve
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using the RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Output-Voltage and Feedback-Resistor Selection
        9. 8.2.2.9  Compensation
        10. 8.2.2.10 Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Development Support
        1. 11.2.1.1 Custom Design With WEBENCH® Tools
    3. 11.3 Documentation Support
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resource
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Simple Small-Signal Model for Peak-Current-Mode Control

Figure 31 is a simple small-signal model that one can use to understand how to design the frequency compensation. A voltage-controlled current source (duty-cycle modulator) supplying current to the output capacitor and load resistor approximates the TPS54388-Q1 power stage. Equation 10 shows the control-to-output transfer function, which consists of a dc gain, one dominant pole, and one ESR zero. The quotient of the change in switch current divided by the change in COMP pin voltage (node c in Figure 31) is the power-stage transconductance. The gm for the TPS54388-Q1 device is 25 S. The low-frequency gain of the power-stage frequency response is the product of the transconductance and the load resistance as shown in Equation 11. As the load current increases and decreases, the low-frequency gain decreases and increases, respectively. This variation with load may seem problematic at first glance, but the dominant pole moves with load current (see Equation 12). The dashed line in the right half of Figure 32 highlights the combined effect. As the load current decreases, the gain increases and the pole frequency lowers, keeping the 0-dB crossover frequency the same for varying load conditions, which makes it easier to design the frequency compensation.

TPS54388-Q1 peak_cur_lvs946.gifFigure 32. Simple Small-Signal Model and Frequency Response for Peak-Current-Mode Control
Equation 10. TPS54388-Q1 eq03_vo_SLVSAH5.gif
Equation 11. TPS54388-Q1 eq06_adc_SLVSAH5.gif
Equation 12. TPS54388-Q1 eq07_fp_SLVSAH5.gif
Equation 13. TPS54388-Q1 eq08_fz_SLVSAH5.gif