SLVSAF1E October   2010  – May 2019 TPS54388-Q1

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Efficiency Curve
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fixed-Frequency PWM Control
      2. 7.3.2 Slope Compensation and Output Current
      3. 7.3.3 Bootstrap Voltage (BOOT) and Low-Dropout Operation
      4. 7.3.4 Error Amplifier
      5. 7.3.5 Voltage Reference
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adjusting the Output Voltage
      2. 7.4.2  Enable Functionality and Adjusting Undervoltage Lockout
      3. 7.4.3  Slow-Start or Tracking Pin
      4. 7.4.4  Sequencing
      5. 7.4.5  Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      6. 7.4.6  Overcurrent Protection
      7. 7.4.7  Frequency Shift
      8. 7.4.8  Reverse Overcurrent Protection
      9. 7.4.9  Synchronize Using the RT/CLK Pin
      10. 7.4.10 Power Good (PWRGD Pin)
      11. 7.4.11 Overvoltage Transient Protection
      12. 7.4.12 Thermal Shutdown
      13. 7.4.13 Small-Signal Model for Loop Response
      14. 7.4.14 Simple Small-Signal Model for Peak-Current-Mode Control
      15. 7.4.15 Small-Signal Model for Frequency Compensation
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Selecting the Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Slow-Start Capacitor
        7. 8.2.2.7  Bootstrap Capacitor Selection
        8. 8.2.2.8  Output-Voltage and Feedback-Resistor Selection
        9. 8.2.2.9  Compensation
        10. 8.2.2.10 Power-Dissipation Estimate
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Third-Party Products Disclaimer
    2. 11.2 Device Support
      1. 11.2.1 Development Support
        1. 11.2.1.1 Custom Design With WEBENCH® Tools
    3. 11.3 Documentation Support
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Community Resource
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Small-Signal Model for Frequency Compensation

The TPS54388-Q1 device uses a transconductance amplifier for the error amplifier and readily supports two of the commonly used frequency-compensation circuits. Figure 33 shows the compensation circuits. The most-likely implementation of Type 2B circuits is in high-bandwidth power-supply designs using low-ESR output capacitors. Type 2A contains one additional high-frequency pole to attenuate high-frequency noise.

TPS54388-Q1 f_compen_lvsa83.gifFigure 33. Types of Frequency Compensation

The design guidelines for TPS54388-Q1 loop compensation are as follows:

  1. Calculate the modulator pole, f(p,mod), and the ESR zero, f(z,mod), using Equation 14 and Equation 15. The output capacitor (C(OUT)) may require derating if the output voltage is a high percentage of the capacitor rating. Use the manufacturer information for the capacitor to derate the capacitor value. Use Equation 16 and Equation 17 to estimate a starting point for the crossover frequency, f(c). Equation 16 is the geometric mean of the modulator pole and the ESR zero, and Equation 17 is the mean of the modulator pole and the switching frequency. Use the lower value of Equation 16 or Equation 17 as the maximum crossover frequency.
  2. Equation 14. TPS54388-Q1 comp_eq1_SLVSAH5.gif
    Equation 15. TPS54388-Q1 comp_eq2_SLVSAH5.gif
    Equation 16. TPS54388-Q1 comp_eq3_SLVSAH5.gif
    Equation 17. TPS54388-Q1 comp_eq4_SLVSAH5.gif
  3. Determine R3 using Equation 18.
  4. Equation 18. TPS54388-Q1 eq09_r3_SLVSAH5.gif

    where

    • gm(ea) is the amplifier gain (245 μS)
    • gm(ps) is the power-stage gain (25 S)
  5. Place a compensation zero at the dominant pole:
  6. Equation 19. TPS54388-Q1 eq07_fp_SLVSAH5.gif
  7. Determine C1 using Equation 20.
  8. Equation 20. TPS54388-Q1 eq10_c1_SLVSAH5.gif

    vertical spacer

  9. C2 is optional. Use it, if necessary, to cancel the zero from the ESR of C(OUT).
  10. Equation 21. TPS54388-Q1 eq11_c2_SLVSAH5.gif