There are two primary considerations for selecting the value of the output capacitor. The output voltage ripple and how the regulator responds to a large change in load current. The output capacitance must be selected based on the more stringent of these criteria.

The desired response to a large change in the load current is the first criteria and is typically the most stringent. A regulator does not respond immediately to a large, fast increase or decrease in load current. The output capacitor supplies or absorbs charge until the regulator responds to the load step. The control loop must sense the change in the output voltage then adjust the peak switch current in response to the change in load. The minimum output capacitance is selected based on an estimate of the loop bandwidth. Typically, the loop bandwidth is near f_SW / 10. Equation 20 estimates the minimum output capacitance necessary.

For this example, the transient load response is specified as a 5% change in V_OUT for a load step of 8 A. Therefore, ΔI_OUT is 8 A and ΔV_OUT is 50 mV. Using this target gives a minimum capacitance of 255 μF. This value does not take the ESR of the output capacitor into account in the output voltage change. For ceramic capacitors, the effect of the ESR can be small enough to be ignored. Aluminum electrolytic and tantalum capacitors have higher ESR that must be considered for load step response.

Equation 20.

where

• ΔI_OUT is the change in output current.
• ΔV_OUT is the allowable change in the output voltage.

In addition to the loop bandwidth, it is possible for the inductor current slew rate to limit how quickly the regulator responds to the load step. For low duty cycle applications, the time it takes for the inductor current to ramp down after a load step down can be the limiting factor. Equation 21 estimates the minimum output capacitance necessary to limit the change in the output voltage after a load step down. Using the 0.22-µH inductance selected gives a minimum capacitance of 59 µF.

Equation 21.

Equation 22 calculates the minimum output capacitance needed to meet the output voltage ripple specification. In this case, the target maximum steady state output voltage ripple is 10 mV. Under this requirement, Equation 22 yields 52 µF.

Equation 22.

where

• ΔI_OUT is the change in output current.
• ΔV_OUT is the allowable change in the output voltage.
• f_SW is the regulators switching frequency.
• V_ORIPPLE is the maximum allowable steady state output voltage ripple.
• I_RIPPLE is the inductor ripple current.

Lastly, if an application does not have a strict load transient response or output ripple requirement, a minimum amount of capacitance is still required to ensure the control loop is stable with the lowest gain ramp setting on the MODE pin. Equation 23 estimates the minimum capacitance needed for loop stability. Equation 23 sets the minimum amount of capacitance by keeping the LC frequency relative to the switching frequency at a minimum value. See Figure 7-3 for the limit versus output voltage with the lowest gain ramp setting of 1 pF. With a 1-V output, the minimum ratio is 35 and with this ratio, Equation 23 gives a minimum capacitance of 141 µF.

Equation 23.

Equation 24 calculates the maximum combined ESR the output capacitors can have to meet the output voltage ripple specification and this shows the ESR must be less than 6 mΩ. In this case, ceramic capacitors are used and the combined ESR of the ceramic capacitors in parallel is much less than is needed to meet the ripple. Capacitors also have limits to the amount of ripple current they can handle without producing excess heat and failing. An output capacitor that can support the inductor ripple current must be specified. The capacitor data sheet specifies the RMS value of the maximum ripple current. Equation 25 can be used to calculate the RMS ripple current the output capacitor must support. For this application, Equation 25 yields 1.2 A and ceramic capacitors typically have a ripple current rating much higher than this.

Equation 24.

Equation 25.

Select X5R and X7R ceramic dielectrics or equivalent for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The output capacitor must also be selected with the DC bias and AC voltage derating taken into account. The derated capacitance value of a ceramic capacitor due to DC voltage bias and AC RMS voltage is usually found on the capacitor manufacturer's website. For this application example, six 100-µF, 10-V, X5R, 1210 ceramic capacitors each with 3 mΩ of ESR are used. With the six parallel capacitors, the estimated effective output capacitance after derating using the capacitor manufacturer's website is 570 µF. There is about -5% DC bias derating at 1 V. This design was able to use less than the calculated minimum because the loop crossover frequency was above the f_SW / 10 estimate as shown in Figure 7-8.