SLVSDV8 July   2017 TPS54424


  1. Features
  2. Applications
    1.     Simplified Schematic
  3. Description
    1.     Efficiency
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-up into Pre-Biased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. High-side MOSFET Overcurrent Protection
        2. Low-side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Custom Design With WEBENCH® Tools
        2.  Switching Frequency
        3.  Output Inductor Selection
        4.  Output Capacitor
        5.  Input Capacitor
        6.  Output Voltage Resistors Selection
        7.  Soft-start Capacitor Selection
        8.  Undervoltage Lockout Set Point
        9.  Bootstrap Capacitor Selection
        10. PGOOD Pull-up Resistor
        11. Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Alternate Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Document Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNV|18
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Sequencing (SS/TRK)

Many of the common power supply sequencing methods can be implemented using the SS/TRK, EN and PGOOD pins.

The sequential method is illustrated in Figure 28 using two TPS54424 or similar devices. The power good of the first device is coupled to the EN pin of the second device which enables the second power supply once the primary supply reaches regulation.

Figure 29 shows the method implementing ratiometric sequencing by connecting the SS/TRK pins of two devices together. The regulator outputs ramp up and reach regulation at the same time. When calculating the soft-start time the current source must be doubled in Equation 4.

TPS54424 fd_seq_startup_slvsdv8-tps54424.gifFigure 28. Sequential Start-Up Sequence
TPS54424 fd_ratio_startup_slvsdv8-tps54424.gifFigure 29. Ratiometric Start-Up Sequence

Ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of RTRT and RTRB shown in Figure 30 to the output of the power supply that needs to be tracked or another voltage reference source. Using Equation 6 and Equation 7, the tracking resistors can be calculated to initiate the VOUT2 slightly before, after or at the same time as VOUT1. Equation 5 is the voltage difference between VOUT1 and VOUT2.

To design a ratiometric start-up in which the VOUT2 voltage is slightly greater than the VOUT1 voltage when VOUT2 reaches regulation, use a negative number in Equation 6 and Equation 7 for deltaV. Equation 5 results in a positive number for applications where the VOUT2 is slightly lower than VOUT1 when VOUT2 regulation is achieved.

The deltaV variable is zero volts for simultaneous sequencing. To minimize the effect of the inherent SS/TRK to FB offset (Vssoffset = 25 mV) in the soft-start circuit and the offset created by the pull-up current source (Iss = 5 μA) and tracking resistors, the Vssoffset and Iss are included as variables in the equations.

To ensure proper operation of the device, the calculated RTRT value from Equation 6 must be greater than the value calculated in Equation 8.

Equation 5. TPS54424 EQ_ratio_simul_deltaV_slvsdc9.gif

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Equation 6. TPS54424 EQ_Rtr_top_slvsdc9.gif

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Equation 7. TPS54424 EQ_Rtr_bot_slvsdc9.gif

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Equation 8. TPS54424 EQ_Rtr_top_min_slvsdc9.gif
TPS54424 fd_ratio_simul_startup_slvsdv8-tps54424.gifFigure 30. Ratiometric and Simultaneous Start-Up Sequence