SLVSDV8 July   2017 TPS54424

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
    1.     Simplified Schematic
  3. 3 Description
    1.     Efficiency
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed Frequency PWM Control
      2. 7.3.2  Continuous Conduction Mode Operation (CCM)
      3. 7.3.3  VIN Pins and VIN UVLO
      4. 7.3.4  Voltage Reference and Adjusting the Output Voltage
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Enable and Adjustable UVLO
      7. 7.3.7  Soft Start and Tracking
      8. 7.3.8  Safe Start-up into Pre-Biased Outputs
      9. 7.3.9  Power Good
      10. 7.3.10 Sequencing (SS/TRK)
      11. 7.3.11 Adjustable Switching Frequency (RT Mode)
      12. 7.3.12 Synchronization (CLK Mode)
      13. 7.3.13 Bootstrap Voltage and 100% Duty Cycle Operation (BOOT)
      14. 7.3.14 Output Overvoltage Protection (OVP)
      15. 7.3.15 Overcurrent Protection
        1. 7.3.15.1 High-side MOSFET Overcurrent Protection
        2. 7.3.15.2 Low-side MOSFET Overcurrent Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Inductor Selection
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Input Capacitor
        6. 8.2.2.6  Output Voltage Resistors Selection
        7. 8.2.2.7  Soft-start Capacitor Selection
        8. 8.2.2.8  Undervoltage Lockout Set Point
        9. 8.2.2.9  Bootstrap Capacitor Selection
        10. 8.2.2.10 PGOOD Pull-up Resistor
        11. 8.2.2.11 Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Alternate Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Document Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RNV|18
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Switching Characteristics

TJ = -40°C to 150°C, V(VIN) = 4.5 V to 17 V (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
EN
EN to start of switching 135 µs
PGOOD
Deglitch time PGOOD going high 272 Cycles
Deglitch time PGOOD going low 16 Cycles
SW
ton_min Minimum on time (1) Measured at 50% to 50% of VIN, L = 1.5 µH, IOUT = 0 A 90 130 ns
toff_min Minimum off time (2) V(BOOT-SW) ≥ 2.6 V 0 ns
RT/CLK
fsw_min Minimum switching frequency (RT mode) R(RT/CLK) = 250 kΩ 200 kHz
Switching frequency (RT mode) R(RT/CLK) = 100 kΩ 450 500 550 kHz
fsw_max Maximum switching frequency (RT mode) R(RT/CLK) = 30.1 kΩ 1.6 MHz
fsw_clk Switching frequency synchronization range (PLL mode) 200 1600 kHz
RT/CLK falling edge to SW rising edge delay (PLL mode) Measure at 500kHz with RT resistor in series with RT/CLK 70 ns
HICCUP
Wait time before hiccup 512 Cycles
Hiccup time before restart 16384 Cycles
(1) Characterized. Not production tested.
(2) Specified by design.