SLVSFW7 September   2022 TPS544C26

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC_OK UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Programmable PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Differential Remote Sense and Internal Feedback Divider
      4. 7.3.4  Set the Output Voltage and VID Table
      5. 7.3.5  Startup and Shutdown
      6. 7.3.6  Dynamic Voltage Slew Rate
      7. 7.3.7  Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
      8. 7.3.8  Loop Compensation
      9. 7.3.9  Set Switching Frequency
      10. 7.3.10 Switching Node (SW)
      11. 7.3.11 Overcurrent Limit and Low-side Current Sense
      12. 7.3.12 Negative Overcurrent Limit
      13. 7.3.13 Zero-Crossing Detection
      14. 7.3.14 Input Overvoltage Protection
      15. 7.3.15 Output Overvoltage and Undervoltage Protection
      16. 7.3.16 Overtemperature Protection
      17. 7.3.17 VR Ready
      18. 7.3.18 Catastrophic Fault Alert: CAT_FAULT#
      19. 7.3.19 Telemetry
      20. 7.3.20 I2C Interface General Description
        1. 7.3.20.1 Setting the I2C Address
        2. 7.3.20.2 I2C Write Protection
        3. 7.3.20.3 I2C Registers With Special Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
      3. 7.4.3 Powering the Device From a 12-V Bus
      4. 7.4.4 Powering the Device From a Split-rail Configuration
    5. 7.5 Programming
      1. 7.5.1 Supported I2C Registers
      2. 7.5.2 Support of Intel SVID Interface
    6. 7.6 Register Maps
      1. 7.6.1  (01h) OPERATION
      2. 7.6.2  (02h) ON_OFF_CONFIG
      3. 7.6.3  (03h) CLEAR_FAULTS
      4. 7.6.4  (15h) STORE_USER_ALL
      5. 7.6.5  (16h) RESTORE_USER_ALL
      6. 7.6.6  (33h) FREQUENCY_SWITCH
      7. 7.6.7  (35h) VIN_ON
      8. 7.6.8  (36h) VIN_OFF
      9. 7.6.9  (40h) VOUT_OV_FAULT_LIMIT
      10. 7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.6.11 (42h) VOUT_OV_WARN_LIMIT
      12. 7.6.12 (43h) VOUT_UV_WARN_LIMIT
      13. 7.6.13 (44h) VOUT_UV_FAULT_LIMIT
      14. 7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
      15. 7.6.15 (46h) IOUT_OC_FAULT_LIMIT
      16. 7.6.16 (4Fh) OT_FAULT_LIMIT
      17. 7.6.17 (50h) OT_FAULT_RESPONSE
      18. 7.6.18 (51h) OT_WARN_LIMIT
      19. 7.6.19 (55h) VIN_OV_FAULT_LIMIT
      20. 7.6.20 (60h) TON_DELAY
      21. 7.6.21 (61h) TON_RISE
      22. 7.6.22 (64h) TOFF_DELAY
      23. 7.6.23 (65h) TOFF_FALL
      24. 7.6.24 (6Bh) PIN_OP_WARN_LIMIT
      25. 7.6.25 (7Ah) STATUS_VOUT
      26. 7.6.26 (7Bh) STATUS_IOUT
      27. 7.6.27 (7Ch) STATUS_INPUT
      28. 7.6.28 (7Dh) STATUS_TEMPERATURE
      29. 7.6.29 (80h) STATUS_MFR_SPECIFIC
      30. 7.6.30 (88h) READ_VIN
      31. 7.6.31 (89h) READ_IIN
      32. 7.6.32 (8Bh) READ_VOUT
      33. 7.6.33 (8Ch) READ_IOUT
      34. 7.6.34 (8Dh) READ_TEMPERATURE_1
      35. 7.6.35 (97h) READ_PIN
      36. 7.6.36 (A0h) SYS_CFG_USER1
      37. 7.6.37 (A2h) I2C_ADDR
      38. 7.6.38 (A3h) SVID_ADDR
      39. 7.6.39 (A4h) IMON_CAL
      40. 7.6.40 (A5h) IIN_CAL
      41. 7.6.41 (A6h) VOUT_CMD
      42. 7.6.42 (A7h) VID_SETTING
      43. 7.6.43 (A8h) I2C_OFFSET
      44. 7.6.44 (A9h) COMP1_MAIN
      45. 7.6.45 (AAh) COMP2_MAIN
      46. 7.6.46 (ABh) COMP1_ALT
      47. 7.6.47 (ACh) COMP2_ALT
      48. 7.6.48 (ADh) COMP3
      49. 7.6.49 (AFh) DVS_CFG
      50. 7.6.50 (B0h) DVID_OFFSET
      51. 7.6.51 (B1h) REG_LOCK
      52. 7.6.52 (B3h) PIN_SENSE_RES
      53. 7.6.53 (B4h) IOUT_NOC_LIMIT
      54. 7.6.54 (B5h) USER_DATA_01
      55. 7.6.55 (B6h) USER_DATA_02
      56. 7.6.56 (BAh) STATUS1_SVID
      57. 7.6.57 (BBh) STATUS2_SVID
      58. 7.6.58 (BCh) CAPABILITY
      59. 7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
      60. 7.6.60 (BEh) VIDOMAX_L
      61. 7.6.61 (C0h) ICC_MAX
      62. 7.6.62 (C1h) TEMP_MAX
      63. 7.6.63 (C2h) PROTOCOL_ID_SVID
      64. 7.6.64 (C6h) VENDOR_ID
      65. 7.6.65 (C8h) PRODUCT_ID
      66. 7.6.66 (C9h) PRODUCT_REV_ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 VINSENP and VINSENN Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 I2C Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS544C26EVM
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.15 Output Overvoltage and Undervoltage Protection

The TPS544C26 device monitors the output voltage (VOSNS − GOSNS) to provide overvoltage (OV) and undervoltage (UV) protection. The Tracking OVF and Tracking UVF thresholds both track to the VOUT setting (commanded by either SVID SetVID command or I2C (A6h) VOUT_CMD) but can be selected independently.

VOUT Tracking UVF

The Table 7-11 shows the available tracking UVF thresholds. When the output voltage (VOSNS − GOSNS) drops below the VOUT setting by the value configured in (44h) VOUT_UV_FAULT_LIMIT register, the tracking UVF comparator detects and an internal UVF Response Delay counter selected in (45h) VOUT_UV_FAULT_RESPONSE register begins. At the same time, the UVF bit in (7Ah) STATUS_VOUT register is set. When the UVF Response Delay expires, the device responds to the UV fault per bit[3] RESTART selection in (45h) VOUT_UV_FAULT_RESPONSE register. With the RESTART bit unset (value "0"), the device latches OFF both high-side and low-side drivers. The latch is cleared with a reset of VCC or by re-toggling the EN pin. With the RESTART bit set (value "1"), the device enters hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts.

The tracking UVF function is enabled only after the soft-start period completes.

During the UVF Response Delay, if the output voltage (VOSNS − GOSNS) rises above the UVF threshold, thus not qualified for a UVF event, the UVF response delay timer resets to zero. When the VOUT drops below the UVF threshold again, the UVF response delay timer re-starts from zero.

The TPS544C26 device also offers tracking UV Warning (UVW) function. The Table 7-12 shows the available tracking UVW thresholds. When the output voltage (VOSNS − GOSNS) drops lower than the VOUT setting by the value configured in (43h) VOUT_UV_WARN_LIMIT register, the tracking UVW comparator detects and the UVW bit in (7Ah) STATUS_VOUT register is set. There is no purpose delay for UVW event.

Table 7-11 VOUT Tracking UV Fault Thresholds
SEL_UVF[1:0]VOUT Tracking UVF Threshold (mV)
00−150
01−200
10−200
11−300
Table 7-12 VOUT Tracking UV Warning Thresholds
SEL_UVW[1:0]VOUT Tracking UVW Threshold (mV)
00−100
01−150
10−200
11−300

VOUT Tracking OVF

The Table 7-13 shows the available tracking OVF thresholds. When the output voltage (VOSNS − GOSNS) rises higher than the VOUT setting by the value configured in (40h) VOUT_OV_FAULT_LIMIT register, the tracking OVF comparator detects and the device responds to the OV fault immediately per bit[3] RESTART selection in (41h) VOUT_OV_FAULT_RESPONSE register. At the same time, the OVF bit in (7Ah) STATUS_VOUT register is set. With the RESTART bit unset (value "0"), the device latches OFF the high-side MOSFET driver and turns on the low-side MOSFET. The low-side MOSFET is kept ON until the sensed low-side negative current reaches the selected negative overcurrent (NOC) limit (see (B4h) IOUT_NOC_LIMIT register). Upon reaching the NOC limit, the low-side MOSFET is turned off, and the high-side MOSFET is turned on, for an on-time determined by PVIN, SEL_NOC_TON bit (see (ADh) COMP3) and fSW setting. After the high-side MOSFET turns off the low-side MOSFET turns on again and the negative current on low-side MOSFET is monitored to compare with the selected NOC limit. The device operates in this cycle until the output voltage is fully discharged. Then the device has high-side MOSFET latched OFF and low-side MOSFET latched ON. The latch is cleared with a reset of VCC or by toggling the EN pin. With the RESTART bit set (value "1"), the device still discharge output voltage by the NOC operation. However, the device activates hiccup mode and re-starts automatically after a hiccup sleep time of 56 ms, without limitation on the number of restart attempts. The hiccup sleep time counter starts right after the OVF trigger.

The tracking OVF function is enabled only after the soft-start period completes.

The TPS544C26 device also offers tracking OV Warning (OVW) function. The Table 7-14 shows the available tracking OVW thresholds. When the output voltage (VOSNS − GOSNS) rises higher than the VOUT setting by the value configured in (42h) VOUT_OV_WARN_LIMIT register, the tracking OVW comparator detects and the OVW bit in (7Ah) STATUS_VOUT register is set. There is no purpose delay for OVW event.

Table 7-13 VOUT Tracking OV Fault Thresholds
SEL_OVF[1:0]VOUT Tracking OVF Threshold (mV)
00+100
01+150
10+200
11+300
Table 7-14 VOUT Tracking OV Warning Thresholds
SEL_OVW[1:0]VOUT Tracking OVW Threshold (mV)
00+100
01+150
10+200
11+300

VOUT Fixed OVF

In parallel with VOUT tracking OVF the TPS544C26 device offers Fixed OVF feature. The Fixed OVF comparator implments a constant reference which is configured in (B4h) IOUT_NOC_LIMIT register and the reference level does not track with the VOUT setting. The Fixed OVF comparator is activated to monitor the output voltage (VOSNS − GOSNS) all the time including power conversion off period (EN = low) and soft-start period. Once the VOUT Fixed OVF is triggered, the OVF bit in (7Ah) STATUS_VOUT register is set, and the device enters NOC operation immediately no matter the power conversion is enabled or not. The device operates in NOC operation to fully discharge the output voltage. Then the device has high-side MOSFET latched OFF and low-side MOSFET latched ON. The latch is cleared with a reset of VCC or by toggling the EN pin. A Fixed OVF event always leads to latch-off response and the selected OVF response in (41h) VOUT_OV_FAULT_RESPONSE register does not affect the response for a Fixed OVF event.

Given the Fixed OVF comparator is always activated the device provides alternate protection to high-side MOSFET damage cases. When the high-side MOSFET is damaged and short PVIN to the SW node, the output voltage (VOSNS − GOSNS) rises quickly. The TPS544C26 device can detect this kind of event and turn on low-side MOSFET to discharge the excess energy, thus protecting the load from damage.

In a case that the commanded VOUT is higher than the Fixed OVF threshold, the device triggers Fixed OV fault and enters the NOC operation immediately. If this scenario happens before soft-start, the device never initiate the soft-start ramp and enters latch-off directly. To avoid this situation, the Fixed OVF feature can be disabled through the bit[2] EN_FIX_OVF in (B4h) IOUT_NOC_LIMIT register.

Table 7-15 VOUT Fixed OV Fault Thresholds
PROTOCOL_ID in (C2h) PROTOCOL_ID_SVIDSEL_FIX_OVF[1] in (B4h) IOUT_NOC_LIMITVOUT Fixed OVF Threshold (V)
PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV)01.5
PROTOCOL_ID = 01b or 10b (VOUT step = 5 mV)11.8
PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV)02.4
PROTOCOL_ID = 00b or 11b (VOUT step = 10 mV)13.0