SLVSFW7 September   2022 TPS544C26

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Internal VCC LDO and Using an External Bias on VCC/VDRV Pin
      2. 7.3.2  Input Undervoltage Lockout (UVLO)
        1. 7.3.2.1 Fixed VCC_OK UVLO
        2. 7.3.2.2 Fixed VDRV UVLO
        3. 7.3.2.3 Programmable PVIN UVLO
        4. 7.3.2.4 Enable
      3. 7.3.3  Differential Remote Sense and Internal Feedback Divider
      4. 7.3.4  Set the Output Voltage and VID Table
      5. 7.3.5  Startup and Shutdown
      6. 7.3.6  Dynamic Voltage Slew Rate
      7. 7.3.7  Adaptive Voltage Positioning (Droop) and DC Load Line (DCLL)
      8. 7.3.8  Loop Compensation
      9. 7.3.9  Set Switching Frequency
      10. 7.3.10 Switching Node (SW)
      11. 7.3.11 Overcurrent Limit and Low-side Current Sense
      12. 7.3.12 Negative Overcurrent Limit
      13. 7.3.13 Zero-Crossing Detection
      14. 7.3.14 Input Overvoltage Protection
      15. 7.3.15 Output Overvoltage and Undervoltage Protection
      16. 7.3.16 Overtemperature Protection
      17. 7.3.17 VR Ready
      18. 7.3.18 Catastrophic Fault Alert: CAT_FAULT#
      19. 7.3.19 Telemetry
      20. 7.3.20 I2C Interface General Description
        1. 7.3.20.1 Setting the I2C Address
        2. 7.3.20.2 I2C Write Protection
        3. 7.3.20.3 I2C Registers With Special Handling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Auto-Skip Eco-mode™ Light Load Operation
      3. 7.4.3 Powering the Device From a 12-V Bus
      4. 7.4.4 Powering the Device From a Split-rail Configuration
    5. 7.5 Programming
      1. 7.5.1 Supported I2C Registers
      2. 7.5.2 Support of Intel SVID Interface
    6. 7.6 Register Maps
      1. 7.6.1  (01h) OPERATION
      2. 7.6.2  (02h) ON_OFF_CONFIG
      3. 7.6.3  (03h) CLEAR_FAULTS
      4. 7.6.4  (15h) STORE_USER_ALL
      5. 7.6.5  (16h) RESTORE_USER_ALL
      6. 7.6.6  (33h) FREQUENCY_SWITCH
      7. 7.6.7  (35h) VIN_ON
      8. 7.6.8  (36h) VIN_OFF
      9. 7.6.9  (40h) VOUT_OV_FAULT_LIMIT
      10. 7.6.10 (41h) VOUT_OV_FAULT_RESPONSE
      11. 7.6.11 (42h) VOUT_OV_WARN_LIMIT
      12. 7.6.12 (43h) VOUT_UV_WARN_LIMIT
      13. 7.6.13 (44h) VOUT_UV_FAULT_LIMIT
      14. 7.6.14 (45h) VOUT_UV_FAULT_RESPONSE
      15. 7.6.15 (46h) IOUT_OC_FAULT_LIMIT
      16. 7.6.16 (4Fh) OT_FAULT_LIMIT
      17. 7.6.17 (50h) OT_FAULT_RESPONSE
      18. 7.6.18 (51h) OT_WARN_LIMIT
      19. 7.6.19 (55h) VIN_OV_FAULT_LIMIT
      20. 7.6.20 (60h) TON_DELAY
      21. 7.6.21 (61h) TON_RISE
      22. 7.6.22 (64h) TOFF_DELAY
      23. 7.6.23 (65h) TOFF_FALL
      24. 7.6.24 (6Bh) PIN_OP_WARN_LIMIT
      25. 7.6.25 (7Ah) STATUS_VOUT
      26. 7.6.26 (7Bh) STATUS_IOUT
      27. 7.6.27 (7Ch) STATUS_INPUT
      28. 7.6.28 (7Dh) STATUS_TEMPERATURE
      29. 7.6.29 (80h) STATUS_MFR_SPECIFIC
      30. 7.6.30 (88h) READ_VIN
      31. 7.6.31 (89h) READ_IIN
      32. 7.6.32 (8Bh) READ_VOUT
      33. 7.6.33 (8Ch) READ_IOUT
      34. 7.6.34 (8Dh) READ_TEMPERATURE_1
      35. 7.6.35 (97h) READ_PIN
      36. 7.6.36 (A0h) SYS_CFG_USER1
      37. 7.6.37 (A2h) I2C_ADDR
      38. 7.6.38 (A3h) SVID_ADDR
      39. 7.6.39 (A4h) IMON_CAL
      40. 7.6.40 (A5h) IIN_CAL
      41. 7.6.41 (A6h) VOUT_CMD
      42. 7.6.42 (A7h) VID_SETTING
      43. 7.6.43 (A8h) I2C_OFFSET
      44. 7.6.44 (A9h) COMP1_MAIN
      45. 7.6.45 (AAh) COMP2_MAIN
      46. 7.6.46 (ABh) COMP1_ALT
      47. 7.6.47 (ACh) COMP2_ALT
      48. 7.6.48 (ADh) COMP3
      49. 7.6.49 (AFh) DVS_CFG
      50. 7.6.50 (B0h) DVID_OFFSET
      51. 7.6.51 (B1h) REG_LOCK
      52. 7.6.52 (B3h) PIN_SENSE_RES
      53. 7.6.53 (B4h) IOUT_NOC_LIMIT
      54. 7.6.54 (B5h) USER_DATA_01
      55. 7.6.55 (B6h) USER_DATA_02
      56. 7.6.56 (BAh) STATUS1_SVID
      57. 7.6.57 (BBh) STATUS2_SVID
      58. 7.6.58 (BCh) CAPABILITY
      59. 7.6.59 (BDh) EXT_CAPABILITY_VIDOMAX_H
      60. 7.6.60 (BEh) VIDOMAX_L
      61. 7.6.61 (C0h) ICC_MAX
      62. 7.6.62 (C1h) TEMP_MAX
      63. 7.6.63 (C2h) PROTOCOL_ID_SVID
      64. 7.6.64 (C6h) VENDOR_ID
      65. 7.6.65 (C8h) PRODUCT_ID
      66. 7.6.66 (C9h) PRODUCT_REV_ID
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Inductor Selection
        2. 8.2.3.2 Input Capacitor Selection
        3. 8.2.3.3 Output Capacitor Selection
        4. 8.2.3.4 VCC/VRDV Bypass Capacitor
        5. 8.2.3.5 BOOT Capacitor Selection
        6. 8.2.3.6 RSENSE Selection
        7. 8.2.3.7 VINSENP and VINSENN Capacitor Selection
        8. 8.2.3.8 VRRDY Pullup Resistor Selection
        9. 8.2.3.9 I2C Address Resistor Selection
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Performance on TPS544C26EVM
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5.1 Supported I2C Registers

The Supported I2C and Default Values Table lists the implemented registers and also the default for the bit behavior and register values.

Table 7-18 Supported I2C and Default Values
Register address Register Name R/W NVM Default Value (Hex) Default Behavior
01h OPERATION R/W NO 00h OPERATION OFF
02h ON_OFF_CONFIG R/W YES 40h Turn ON/OFF by EN pin only
03h CLEAR_FAULTS W NO N/A Clear all faults
15h STORE_USER_ALL W NO N/A Stores all current storable register settings into NVM
16h RESTORE_USER_ALL W NO N/A Restores all storable register settings from NVM
33h FREQUENCY_SWITCH R/W YES 01h Switching frequency is set to 800 kHz
35h VIN_ON R/W YES 03h ON threshold is determined by both PVIN and VCC conditions. Both PVIN > 2.55 V and VCC > 3.8 V conditions have to be satisfied to enable the power conversion.
36h VIN_OFF R/W YES 07h OFF threshold is determined by both PVIN and VCC conditions. Either PVIN ≤ 2.3 V or VDRV ≤ 3.4 V disables the power conversion.
40h VOUT_OV_FAULT_LIMIT R/W YES 02h VOUT Tracking OV Fault threshold = +200 mV
41h VOUT_OV_FAULT_RESPONSE R/W YES 00h Latch-off after a fault
42h VOUT_OV_WARN_LIMIT R/W YES 01h VOUT Tracking OV Warning threshold = +150 mV
43h VOUT_UV_WARN_LIMIT R/W YES 01h VOUT Tracking UV Warning threshold = −150 mV
44h VOUT_UV_FAULT_LIMIT R/W YES 02h VOUT Tracking UV Fault threshold = −200 mV
45h VOUT_UV_FAULT_RESPONSE R/W YES 02h Latch-off after a fault, and the response delay before disabling the power conversion is 64 µs
46h IOUT_OC_FAULT_LIMIT R/W YES 09h Low-side valley current limiting threshold = 35 A
4Fh OT_FAULT_LIMIT R/W YES 07h Programmable OT Fault threshold = 150 °C
50h OT_FAULT_RESPONSE R/W YES 00h Latch-off after a fault
51h OT_WARN_LIMIT R/W YES 06h Programmable OT Warning threshold = 125 °C
55h VIN_OV_FAULT_LIMIT R/W YES 01h PVIN OV Fault threshold = 18.5 V
60h TON_DELAY R/W YES 00h 0.5 ms delay when a start condition is received (as programmed by the ON_OFF_CONFIG register) until the output voltage starts to rise
61h TON_RISE R/W YES 00h 1 ms from when the output starts to rise until the output voltage has entered the regulation band
64h TOFF_DELAY R/W YES 00h 0 ms from when a stop condition is received (as programmed by the ON_OFF_CONFIG register) until the unit starts the soft-stop operation
65h TOFF_FALL R/W YES 00h 0.5 ms from the end of the turn-off delay time until the internal reference DAC is commanded to 0 mV
6Bh PIN_OP_WARN_LIMIT R/W YES 03h Maximum PIN (input power) threshold = 360 W
7Ah STATUS_VOUT R/W NO N/A Current status
7Bh STATUS_IOUT R/W NO N/A Current status
7Ch STATUS_INPUT R/W NO N/A Current status
7Dh STATUS_TEMPERATURE R/W NO N/A Current status
80h STATUS_MFR_SPECIFIC R/W NO N/A Current status
88h READ_VIN R NO N/A Measured input voltage on pin 4 VINSENM
89h READ_IIN R NO N/A Measured input current over the external sensing resistor
8Bh READ_VOUT R NO N/A Measured output voltage
8Ch READ_IOUT R NO N/A Measured output current
8Dh READ_TEMPERATURE_1 R NO N/A Measured Controller die temperature
97h READ_PIN R NO N/A Calculated input power, the product of the measured input voltage and input current
A0h SYS_CFG_USER1 R/W YES 10h

Operation mode under light load condition is DCM

VOUT is controlled by SVID bus only

Soft-stop feature is enabled

VR Ready delay = 0 ms

I2C address is set by pin 29 pin strap detection
A2h I2C_ADDR R/W YES N/A

Bit[7] = 0b, reserved for TI usage

I2C address saved in NVM is 77h. However, after initial power-on, the effective I2C address shown in this field is determined by the resistor on pin 29
A3h SVID_ADDR R/W YES 00h Device address for SVID communication is set to 00h
A4h IMON_CAL R/W YES 78h

IMON gain calibration = 0%

IMON offset calibration = 0 A
A5h IIN_CAL R/W YES 78h

IIN gain calibration = 0%

IIN offset calibration = 0 A
A6h VOUT_CMD R/W YES ABh Default VOUT setting saved in VOUT_CMD is 1.1V. The VOUT_CMD does not control VOUT unless VOUT_CTRL = 10b or 11b
A7h VID_SETTING R NO N/A After initial power-on, this register shows a value reflecting the last commanded VOUT either from SVID bus or I2C bus
A8h I2C_OFFSET R/W YES 00h I2C OFFSET = 0 mV
A9h COMP1_MAIN R/W YES 4Ah

AC Gain = 2

AC Load Line = 7
AAh COMP2_MAIN R/W YES 19h

Integration gain = 2

Integration time constant = 4.25 µs

Ramp Amplitude = 60 mV
ABh COMP1_ALT R/W YES 23h This register is not activated in the TPS544C26 device and affects nothing.
ACh COMP2_ALT R/W YES A2h This register is not activated in the TPS544C26 device and affects nothing.
ADh COMP3 R/W YES 02h

Bit[7] = 0b, reserverd for TI usage

Force DCM during soft-start enable/disable bit = disabled

On-time during NOC (Negative OC) operation = longer tON_NOC

LOUT (output inductor value) for current sensing circuit = 100 nH

DC Load Line = 0.75 mΩ
AFh DVS_CFG R/W YES 06h Dynamic voltage change fast slew rate configuration = 10 mV/µs
B0h DVID_OFFSET R/W YES 00h

DVID Up positive DAC offset = 0 mV

DVID Down positive DAC offset = 0 mV
B1h REG_LOCK W YES N/A The user-accessible registers (not including B1h) are “write protected” and by default. User can still read back from registers
B3h PIN_SENSE_RES R/W YES 05h Input power sense resistor is 0.5 mΩ. This also sets the Maximum IIN to 40 A with IIN_LSB = 0.15625 A
B4h IOUT_NOC_LIMIT R/W YES 05h

VOUT Fixed OV Fault threshold = 1.5 V

VOUT Fixed OV Fault enable/disable bit = enabled

Negative OC limit = −15 A when ICC_MAX ≥ 15 A or −7.5 A when ICC_MAX < 10 A
B5h USER_DATA_01 R/W YES 00h Bit[7:4]: For user to store manufacturer specific information
B6h USER_DATA_02 R/W YES 00h Bit[7:5]: For user to store manufacturer specific information
BAh STATUS1_SVID R/W YES N/A A direct copy of the bits of SVID STATUS_1 register
BBh STATUS2_SVID R/W YES N/A A direct copy of the bits of SVID STATUS_2 register
BCh CAPABILITY R NO FBh A direct copy of the bits of SVID CAPABILITY register
BDh EXT_CAPABILITY_VIDOMAX_H R/W YES 04h A direct copy of the bits of SVID VIDOMAX_H_CAPA register
BEh VIDOMAX_L R/W YES B6h 9-bit VIDoMAX = 1.155 V
C0h ICC_MAX R/W YES 05h ICC_MAX = 30 A
C1h TEMP_MAX R/W YES 06h TEMP_MAX = 125 °C while controls SVID "ThermAlert" bit
C2h PROTOCOL_ID_SVID R/W YES 63h

PROTOCOL_ID_SVID = 07h (VR13, VOUT step 5 mV)

Vboot = 1.1 V

Respond to SVID All-call address both 0Eh and 0Fh
C6h VENDOR_ID R NO 22h SVID VENDOR_ID = 22h. This vendor ID is assigned to Texas Instruments by Intel, to identify the VR vendor.
C8h PRODUCT_ID R NO 13h TPS544C26 Product ID = 13h
C9h PRODUCT_REV_ID R NO 02h TPS544C26 current device revision = PG2.1