SLVSBI5A May 2013 – October 2014 TPS54531
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS54531 device is typically used as a step-down converter, which converts a voltage from 3.5 V to 28 V to a lower voltage. WEBENCH® software is available to aid in the design and analysis of circuits.
For additional design needs, see the following devices:
|I(max)||2 A||2 A||2 A||5 A||3.5 A|
|Input voltage range||3.5 to 28 V||3.5 to 28 V||3.5 to 28 V||3.5 to 28 V||3.5 to 28 V|
|Switching frequency (typ)||570 kHz||1000 kHz||285 kHz||570 kHz||1000 kHz|
|Switch current limit (min)||2.3 A||2.3 A||2.3 A||5.5 A||4.2 A|
|Pin and package||8SOIC||8SOIC||8SOIC||8SO PowerPAD™||8SO PowerPAD™|
For this design example, use the values listed in Table 2 as the input parameters
|DESIGN PARAMETER||EXAMPLE VALUE|
|Input voltage range||8 to 28 V|
|Output voltage||5 V|
|Transient response, 2.5-A load step||ΔVOUT = ±5%|
|Input ripple voltage||400 mV|
|Output ripple voltage||30 mV|
|Output current rating||5 A|
|Operating Frequency||570 kHz|
The following design procedure can be used to select component values for the TPS54531 device. Alternately, the WEBENCH software can be used to generate a complete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensive database of components when generating a design. This section presents a simplified discussion of the design process.
The switching frequency for the TPS54531 is fixed at 570 kHz.
The output voltage of the TPS54531 device is externally adjustable using a resistor divider network. As shown in Figure 10, this divider network is comprised of R5 and R6. The relationship of the output voltage to the resistor divider is given by Equation 4 and Equation 5:
Select a value of R5 to be approximately 10 kΩ. Slightly increasing or decreasing the value of R5 can result in closer output-voltage matching when using standard value resistors. In this design, R5 = 10.2 kΩ and R6 = 1.96 kΩ, resulting in a 4.96 V output voltage. The 51.1-Ω resistor, R4, is provided as a convenient location to break the control loop for stability testing.
The undervoltage lockout (UVLO) can be adjusted using the external voltage divider network of R1 and R2. R1 is connected between the VIN and EN pins of the TPS54531 device and R2 is connected between the EN and GND pins. The UVLO has two thresholds, one for power up when the input voltage is rising and one for power down or brown outs when the input voltage is falling. For the design example, the minimum input voltage is 8 V. Therefore the start voltage threshold is set to 7 V with 2-V hysteresis. Use Equation 1 and Equation 2 to calculate the values for the upper and lower resistor values of R1 and R2.
The TPS54531 device requires an input decoupling capacitor and, depending on the application, a bulk input capacitor. The typical recommended value for the decoupling capacitor is 10 μF. A high-quality ceramic type X5R or X7R is recommended. The voltage rating should be greater than the maximum input voltage. A smaller value can be used as long as all other requirements are met; however 10 μF has been shown to work well in a wide variety of circuits. Additionally, some bulk capacitance may be required, especially if the TPS54531 circuit is not located within about 2 inches from the input voltage source. The value for this capacitor is not critical but should be rated to handle the maximum input voltage including ripple voltage, and should filter the output so that input ripple voltage is acceptable. For this design two 4.7-μF capacitors are used for the input decoupling capacitor. The capacitors are X7R dielectric rated for 50 V. The equivalent series resistance (ESR) is approximately 2 mΩ and the current rating is 3 A. Additionally, a small 0.01 μF capacitor is included for high frequency filtering.
Use Equation 6 to calculate the input ripple voltage.
The maximum RMS ripple current must also be checked. For worst case conditions, use Equation 7 to calculate the maximum-RMS input ripple current, ICIN(RMS).
In this case, the input ripple voltage is 243 mV and the RMS ripple current is 2.5 A.
The actual input voltage ripple is greatly affected by parasitics associated with the layout and the output impedance of the voltage source.
The actual input voltage ripple for this circuit is listed in Table 2 and is larger than the calculated value. This measured value is still below the specified input limit of 300 mV. The maximum voltage across the input capacitors would be VIN(MAX) + ΔVIN / 2. The selected bulk and bypass capacitors are each rated for 50 V and the ripple current capacity is greater than 3 A, both providing ample margin. The maximum ratings for voltage and current must not be exceeded under any circumstance.
Two components must be selected for the output filter, LOUT and COUT. Because the TPS54531 is an externally compensated device, a wide range of filter component types and values can be supported.
To calculate the minimum value of the output inductor, use Equation 8
In general, this value is at the discretion of the designer; however, the following guidelines may be used. For designs using low-ESR output capacitors such as ceramics, a value as high as KIND = 0.3 may be used. When using higher ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.3 and the minimum inductor value is calculated as 4.8 μH. For this design, a close, standard value was chosen: 4.7 μH.
For the output filter inductor, do not exceed the RMS current and saturation current ratings. Use Equation 9 to calculate the inductor ripple current (Iripple).
Use Equation 10 to calculate the RMS inductor current.
Use Equation 11 to calculate the peak inductor current.
For this design, the RMS inductor current is 5.03 A and the peak inductor current is 5.96 A. The selected inductor is a Wurth 4.7 μH. This inductor has a saturation current rating of 19 A and an RMS current rating of 7 A, which meets these requirements. Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to allow, so long as the other design requirements are met. Larger value inductors have lower AC current and result in lower output voltage ripple, while smaller inductor values will increase AC current and output voltage ripple. In general, inductor values for use with the TPS54531 device are in the range of 1 μH to 47 μH.
Selecting the value of the output capacitor is based on three primary considerations. The output capacitor determines the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current. The output capacitance must be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criteria. The output capacitor must supply the load with current when the regulator can not. This situation occurs if desired hold-up times occur for the regulator where the output capacitor must hold the output voltage above a certain level for a specified amount of time after the input power is removed. The regulator is also temporarily not able to supply sufficient output current if a large, fast increase occurs in the current needs of the load, such as a transition from no load to full load. The regulator usually requires two or more clock cycles for the control loop to respond to the change in load current and output voltage and adjust the duty cycle to react to the change. The output capacitor must be sized to supply the extra current to the load until the control loop responds to the load change. The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only allowing a tolerable amount of drop in the output voltage. Use Equation 12 to calculate minimum output capacitance (CO) required in this case.
For this example, the transient load response is specified as a 5% change in VOUT for a load step of 2.5 A. For this example, ΔIOUT = 2.5 A and ΔVOUT = 0.05 x 5 = 0.25 V. Using these values results in a minimum capacitance of 35 μF. This value does not consider the ESR of the output capacitor in the output voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
Use Equation 13 to calculate the minimum output capacitance needed to meet the output voltage ripple specification. In this case, the maximum output voltage ripple is 30 mV. Under this requirement Equation 13, yields 14 µF.
Use Equation 14 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple specification. Equation 14 indicates the ESR should be less than 15.6 mΩ. In this case, the ESR of the ceramic capacitor is much smaller than 15.6 mΩ.
Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases this minimum value. For this example, two 47-μF 10-V X5R ceramic capacitors with 3 mΩ of ESR are used. Capacitors generally have limits to the amount of ripple current they can handle without failing or producing excess heat. An output capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the RMS (root mean square) value of the maximum ripple current. Use Equation 15 to calculate the RMS ripple current that the output capacitor must support. For this application, Equation 15 yields 554 mA.
Several possible methods exist to design closed loop compensation for DC-DC converters. For the ideal current mode control, the design equations can be easily simplified. The power stage gain is constant at low frequencies, and rolls off at –20 dB/decade above the modulator pole frequency. The power stage phase is 0 degrees at low frequencies and begins to fall one decade below the modulator pole frequency reaching a minimum of –90 degrees one decade above the modulator pole frequency. Use Equation 16 to calculate the modulator pole frequency.
For the TPS54531 device, most circuits have relatively high amounts of slope compensation. As more slope compensation is applied, the power stage characteristics deviate from the ideal approximations. The phase loss of the power stage will now approach –180 degrees, making compensation more difficult. The power stage transfer function can be solved but it requires a tedious calculation. Use the PSpice model to accurately model the power-stage gain and phase so that a reliable compensation circuit can be designed. Alternately, a direct measurement of the power stage characteristics can be used. That is the technique used in this design procedure. For this design, the calculate values are as follows:
L1 = 4.7 µH
C8 and C9 = 47 µF (each)
ESR = 3 mΩ
Figure 11 shows the power stage characteristics.
For this design, the intended crossover frequency is 20 kHz. From the power stage gain and phase plots, the gain at 20 kHz is 5.1 dB and the phase is about –100 degrees. For 60 degrees of phase margin, additional phase boost from a feed-forward capacitor in parallel with the upper resistor of the voltage set point divider is not needed. R3 sets the gain of the compensated error amplifier to be equal and opposite the power stage gain at crossover. Use Equation 17 to calculate the required value of R3.
To maximize phase gain, the compensator zero is placed one decade below the crossover frequency of 20 kHz. Use Equation 18 to calculate the required value for C6.
To maximize phase gain the high frequency pole is placed one decade above the crossover frequency of 20 kHz. The pole can also be useful to offset the ESR of aluminum electrolytic output capacitors. Use Equation 19 to calculate the value for C7.
For this design, the calculated values are as follows:
R3 = 37.4 kΩ
C6 = 2200 pF
C7 = 22 pF
Every TPS54531 design requires a bootstrap capacitor, C4. The bootstrap capacitor value must be 0.1 μF. The bootstrap capacitor is located between the PH and BOOT pins. The bootstrap capacitor should be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
The TPS54531 device sis designed to operate using an external catch diode between the PH and GND pins. The selected diode must meet the absolute maximum ratings for the application. The reverse voltage must be higher than the maximum voltage at the PH pin, which is VIN(MAX) + 0.5 V. Peak current must be greater than IO(MAX) plus on half the peak-to-peak inductor current. The forward-voltage drop should be small for higher efficiencies. The catch diode conduction time is (typically) longer than the high-side FET on time, so attention paid to diode parameters can make a marked improvement in overall efficiency. Additionally, check that the selected device is capable of dissipating the power losses. For this design, a CDBC540-G was selected, with a reverse voltage of 40 V, forward current of 5 A, and a forward-voltage drop of 0.55 V.
The slow-start capacitor determines the minimum amount of time required for the output voltage to reach the nominal programmed value during power up which is useful if a load requires a controlled voltage slew rate. The slow-start capacitor is also used if the output capacitance is very large and requires large amounts of current to quickly charge the capacitor to the output voltage level. The large currents necessary to charge the capacitor may make the TPS54531 device reach the current limit. Excessive current draw from the input power supply may cause the input voltage rail to sag. Limiting the output voltage slew rate solves both of these problems. Use Equation 3 to calculate the value of the slow-start capacitor. For the example circuit, the slow-start time is not too critical because the output capacitor value is 2 × 47 μF which does not require much current to charge to 5 V. The example circuit has the slow-start time set to an arbitrary value of 4 ms which requires a 10-nF capacitor. For the TPS54531 device, ISS is 2 µA and Vref is 0.8 V.
Because of the internal design of the TPS54531 device, any give voltage has both upper and lower output voltage limits for any given input voltage. The upper limit of the output-voltage set point is constrained by the maximum duty cycle of 91% and is calculated with Equation 20. The equation assumes the maximum ON resistance for the internal high-side FET.
The lower limit is constrained by the minimum controllable on time which may be as high as 130 ns. The approximate minimum output voltage for a given input voltage and minimum load current is given by Equation 21.
This equation assumes nominal on-resistance for the high-side FET and accounts for worst case variation of operating frequency set point. Any design operating near the operational limits of the device should be carefully checked to ensure proper functionality.
The following formulas show how to estimate the device power dissipation under continuous-conduction mode (CCM) operations. These formulas should not be used if the device is working in the discontinuous-conduction mode (DCM) or pulse-skipping Eco-modeTM.
The device power dissipation includes:
For given TA:
For given TJMAX = 150°C: