SLUSCK1C July   2016  – June 2018 TPS546C20A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  2-Phase Application
      2. 7.3.2  Linear Regulators BP3 and BP6
      3. 7.3.3  Input Undervoltage Lockout (UVLO)
      4. 7.3.4  Turnon and Turnoff Delay and Sequencing
      5. 7.3.5  Voltage Reference
      6. 7.3.6  Differential Remote Sense and Compensation
      7. 7.3.7  Set Output Voltage and Adaptive Voltage Scaling (AVS)
        1. 7.3.7.1 VOUT_COMMAND
        2. 7.3.7.2 VREF_TRIM
        3. 7.3.7.3 MARGIN
        4. 7.3.7.4 Use VSEL to Set Default Output Voltage
      8. 7.3.8  Reset VOUT
      9. 7.3.9  Switching Frequency and Synchronization
        1. 7.3.9.1 Synchronization
          1. 7.3.9.1.1 Stand-Alone Device
          2. 7.3.9.1.2 Master-Slave Configuration
          3. 7.3.9.1.3 SYNC Fault
      10. 7.3.10 Current Sharing
      11. 7.3.11 Soft-Start Time and TON_RISE Command
      12. 7.3.12 Prebiased Output Start-Up
      13. 7.3.13 Soft-Stop time and TOFF_FALL Command
      14. 7.3.14 Output Current Telemetry and Low-Side MOSFET Overcurrent Protection
        1. 7.3.14.1 Output Current Telemetry
        2. 7.3.14.2 Low-Side MOSFET Overcurrent Protection
        3. 7.3.14.3 Negative Overcurrent Protection
      15. 7.3.15 High-Side MOSFET Short-Circuit Protection
      16. 7.3.16 Die Temperature Telemetry and Overtemperature Protection
      17. 7.3.17 Output Voltage Telemetry and Over-/Under-voltage Protection
        1. 7.3.17.1 Output Voltage Telemetry
        2. 7.3.17.2 Output Overvoltage and Undervoltage Protection
      18. 7.3.18 TON_MAX Fault
      19. 7.3.19 Power Good (PGOOD) Indicator
      20. 7.3.20 Fault Protection Responses
      21. 7.3.21 Switching Node
      22. 7.3.22 PMBus General Description
      23. 7.3.23 PMBus Address
      24. 7.3.24 PMBus Connections
      25. 7.3.25 Auto ARA (Alert Response Address) Response
    4. 7.4 Device Functional Modes
      1. 7.4.1 Continuous Conduction Mode
      2. 7.4.2 Operation with CNTL Signal Control
      3. 7.4.3 Operation with OPERATION Control
      4. 7.4.4 Operation with CNTL and OPERATION Control
    5. 7.5 Programming
      1. 7.5.1 Supported PMBus Commands
    6. 7.6 Register Maps
      1. 7.6.1  OPERATION (01h)
        1. 7.6.1.1 On Bit
        2. 7.6.1.2 Off Bit
        3. 7.6.1.3 Margin Bit
      2. 7.6.2  ON_OFF_CONFIG (02h)
        1. 7.6.2.1 pu Bit
        2. 7.6.2.2 cmd Bit
        3. 7.6.2.3 cpr Bit
        4. 7.6.2.4 pol Bit
        5. 7.6.2.5 cpa Bit
      3. 7.6.3  CLEAR_FAULTS (03h)
      4. 7.6.4  WRITE_PROTECT (10h)
        1. 7.6.4.1 bit5
        2. 7.6.4.2 bit6
        3. 7.6.4.3 bit7
      5. 7.6.5  STORE_DEFAULT_ALL (11h)
      6. 7.6.6  RESTORE_DEFAULT_ALL (12h)
      7. 7.6.7  STORE_USER_ALL (11h)
      8. 7.6.8  RESTORE_USER_ALL (12h)
      9. 7.6.9  CAPABILITY (19h)
      10. 7.6.10 SMBALERT_MASK (1Bh)
      11. 7.6.11 VOUT_MODE (20h)
        1. 7.6.11.1 Mode Bit
        2. 7.6.11.2 Exponent Bit
      12. 7.6.12 VOUT_COMMAND (21h)
        1. 7.6.12.1 Exponent
        2. 7.6.12.2 Mantissa
      13. 7.6.13 VOUT_MAX (24h)
        1. 7.6.13.1 Exponent
        2. 7.6.13.2 Mantissa
      14. 7.6.14 VOUT_TRANSITION_RATE (27h)
        1. 7.6.14.1 Exponent
        2. 7.6.14.2 Mantissa
      15. 7.6.15 VOUT_SCALE_LOOP (29h)
        1. 7.6.15.1 Exponent
        2. 7.6.15.2 Mantissa
      16. 7.6.16 VOUT_MIN (2Bh)
        1. 7.6.16.1 Exponent
        2. 7.6.16.2 Mantissa
      17. 7.6.17 VIN_ON (35h)
        1. 7.6.17.1 Exponent
        2. 7.6.17.2 Mantissa
      18. 7.6.18 VIN_OFF (36h)
        1. 7.6.18.1 Exponent
        2. 7.6.18.2 Mantissa
      19. 7.6.19 IOUT_CAL_OFFSET (39h)
        1. 7.6.19.1 Exponent
        2. 7.6.19.2 Mantissa
      20. 7.6.20 VOUT_OV_FAULT_RESPONSE (41h)
        1. 7.6.20.1 RSP[1] Bit
        2. 7.6.20.2 RS[2:0] Bits
        3. 7.6.20.3 TD[2:0] Bits
      21. 7.6.21 VOUT_UV_FAULT_RESPONSE (45h)
        1. 7.6.21.1 RSP[1] Bit
        2. 7.6.21.2 RS[2:0] Bits
        3. 7.6.21.3 TD[2:0] Bits
      22. 7.6.22 IOUT_OC_FAULT_LIMIT (46h)
        1. 7.6.22.1 Exponent
        2. 7.6.22.2 Mantissa
      23. 7.6.23 IOUT_OC_FAULT_RESPONSE (47h)
        1. 7.6.23.1 RSP[1:0] Bits
        2. 7.6.23.2 RS[2:0] Bits
        3. 7.6.23.3 TD[2:0] Bits
      24. 7.6.24 IOUT_OC_WARN_LIMIT (4Ah)
        1. 7.6.24.1 Exponent
        2. 7.6.24.2 Mantissa
      25. 7.6.25 OT_FAULT_LIMIT (4Fh)
        1. 7.6.25.1 Exponent
        2. 7.6.25.2 Mantissa
      26. 7.6.26 OT_FAULT_RESPONSE (50h)
        1. 7.6.26.1 RSP[1] Bit
        2. 7.6.26.2 RS[2:0] Bits
        3. 7.6.26.3 TD[2:0] Bits
      27. 7.6.27 OT_WARN_LIMIT (51h)
        1. 7.6.27.1 Exponent
        2. 7.6.27.2 Mantissa
      28. 7.6.28 TON_DELAY (60h)
        1. 7.6.28.1 Exponent
        2. 7.6.28.2 Mantissa
      29. 7.6.29 TON_RISE (61h)
        1. 7.6.29.1 Exponent
        2. 7.6.29.2 Mantissa
      30. 7.6.30 TON_MAX_FAULT_LIMIT (62h)
        1. 7.6.30.1 Exponent
        2. 7.6.30.2 Mantissa
      31. 7.6.31 TON_MAX_FAULT_RESPONSE (63h)
        1. 7.6.31.1 RSP[1] Bit
        2. 7.6.31.2 RS[2:0] Bits
        3. 7.6.31.3 TD[2:0] Bits
      32. 7.6.32 TOFF_DELAY (64h)
        1. 7.6.32.1 Exponent
        2. 7.6.32.2 Mantissa
      33. 7.6.33 TOFF_FALL (65h)
        1. 7.6.33.1 Exponent
        2. 7.6.33.2 Mantissa
      34. 7.6.34 STATUS_BYTE (78h)
      35. 7.6.35 STATUS_WORD (79h)
      36. 7.6.36 STATUS_VOUT (7Ah)
      37. 7.6.37 STATUS_IOUT (7Bh)
      38. 7.6.38 STATUS_INPUT (7Ch)
      39. 7.6.39 STATUS_TEMPERATURE (7Dh)
      40. 7.6.40 STATUS_CML (7Eh)
      41. 7.6.41 STATUS_MFR_SPECIFIC (80h)
      42. 7.6.42 READ_VOUT (8Bh)
        1. 7.6.42.1 Exponent
        2. 7.6.42.2 Mantissa
      43. 7.6.43 READ_IOUT (8Ch)
        1. 7.6.43.1 Exponent
        2. 7.6.43.2 Mantissa
      44. 7.6.44 READ_TEMPERATURE_1 (8Dh)
        1. 7.6.44.1 Exponent
        2. 7.6.44.2 Mantissa
      45. 7.6.45 PMBUS_REVISION (98h)
      46. 7.6.46 IC_DEVICE_ID (ADh)
      47. 7.6.47 IC_DEVICE_REV (AEh)
      48. 7.6.48 MFR_SPECIFIC_00 (D0h)
      49. 7.6.49 VREF_TRIM (MFR_SPECIFIC_04) (D4h)
      50. 7.6.50 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)
      51. 7.6.51 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)
      52. 7.6.52 PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h)
      53. 7.6.53 OPTIONS (MFR_SPECIFIC_21) (E5h)
        1. 7.6.53.1  DIS_NEGILIM Bit
        2. 7.6.53.2  EN_RESET_B Bit
        3. 7.6.53.3  EN_ADC_CNTL Bit
        4. 7.6.53.4  VSM Bit
        5. 7.6.53.5  DLO Bit
        6. 7.6.53.6  AVG_PROG[1:0] Bits
        7. 7.6.53.7  EN_AUTO_ARA Bit
        8. 7.6.53.8  READ_VOUT_RANGE[1:0] Bits
        9. 7.6.53.9  EN_DRV_IV_VSEL Bit
        10. 7.6.53.10 RST_VOUT_oSD Bit
        11. 7.6.53.11 DIS_VSEL Bit
        12. 7.6.53.12 RSMLO_VAL Bit
        13. 7.6.53.13 RSMHI_VAL Bit
      54. 7.6.54 MISC_CONFIG_OPTIONS (MFR_SPECIFIC_32) (F0h)
        1. 7.6.54.1 OV_RESP_SEL Bit
        2. 7.6.54.2 HSOC_USER_TRIM[1:0] Bits
        3. 7.6.54.3 EN_AVS_USER Bit
        4. 7.6.54.4 FORCE_SYNC_OUT Bit
        5. 7.6.54.5 FORCE_SYNC_IN Bit
        6. 7.6.54.6 SYNC_FAULT_DIS Bit
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 4.5-V to 18-V Input, 1-V Typical Output, 35-A Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Switching Frequency Selection
          3. 8.2.1.2.3  Inductor Selection
          4. 8.2.1.2.4  Output Capacitor Selection
          5. 8.2.1.2.5  Output Voltage Deviation During Load Transient
          6. 8.2.1.2.6  Output Voltage Ripple
          7. 8.2.1.2.7  Input Capacitor Selection
          8. 8.2.1.2.8  AVIN, BP6, BP3 Bypass Capacitor
          9. 8.2.1.2.9  Bootstrap Capacitor Selection
          10. 8.2.1.2.10 R-C Snubber
          11. 8.2.1.2.11 Output Voltage Setting and Frequency Compensation Selection
          12. 8.2.1.2.12 Key PMBus Parameter Selection
          13. 8.2.1.2.13 Enable, UVLO
          14. 8.2.1.2.14 Soft-Start Time
          15. 8.2.1.2.15 Overcurrent Threshold and Response
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Mounting and Thermal Profile Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Development Support
      1. 11.1.1 Custom Design With WEBENCH® Tools
      2. 11.1.2 Texas Instruments Fusion Digital Power Designer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVF|40
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.20 Fault Protection Responses

Table 4 summarizes the various fault protections and associated responses.

Table 4. Fault Protection Summary

FAULT or WARN PROGRAMMING FAULT RESPONSE SETTING FET BEHAVIOR ACTIVE DURING TON_RISE SOURCE OF SMBALERT SMBALERT MASKABLE PGOOD
Internal Over Temp Fault OT_FAULT_LIMIT (4Fh) Latch-off Both FETs off Yes Yes Yes Low
Restart Both FETs off, then restart after cooling down(1) Low
Ignore FETs still controlled by PWM High
Internal Over Temp Warn OT_WARN_LIMIT (51h) Latch-off or Restart on Fault PWM maintains control of FETs Yes Yes Yes Low
Ignore Fault High
Bandgap Over Temp Fault Threshold fixed internally Latch-off Both FETs off Yes Yes Yes Low
Restart Both FETs off, then restart after cooling down(1)
Ignore Both FETs off, then restart after cooling down(2)
Low-Side OC Fault IOUT_OC_FAULT_LIMIT (46h) Latch-off 3 PWM counts, then both FETs off Yes Yes Yes Low
Restart 3 PWM counts, then both FETs off, restart after 7×TON_RISE Low
Ignore FETs still controlled by PWM High
Low-Side OC Warn IOUT_OC_WARN_LIMIT Latch-off or Restart on Fault PWM maintains control of FETs Yes Yes Yes Low
Ignore Fault High
High-Side OC Fault HSOC_USER_TRIM[1:0] Bits Latch-off 3 PWM counts, then both FETs off Yes Yes Yes Low
Restart 3 PWM counts, then both FETs off, restart after 7 × TON_RISE Low
Ignore Cycle-by-cycle peak current limit High
VOUT OV Fault PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h) Latch-off High-side FET OFF, low-side FET response configured byOV_RESP_SEL Bit: latch ON or turn on till FB drops below 0.2 V Yes Yes Yes Low
Restart High-side FET OFF, low-side FET response configured byOV_RESP_SEL Bit: latch ON or turn on till FB drops below 0.2 V. Then restart after 7 × TON_RISE
Ignore PWM maintains control of FETs
VOUT OV Warn PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h) Latch-off or Restart on Fault PWM maintains control of FETs Yes Yes Yes Low
Ignore Fault
VOUT UV Fault PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h) Latch-off Both FETs off No Yes Yes Low
Restart Both FETs off, then restart after 7×TON_RISE
Ignore PWM maintains control of FETs
VOUT UV Warn PCT_OV_UV_WRN_FLT_LIMITS (MFR_SPECIFIC_07) (D7h) Latch-off or Restart on Fault PWM maintains control of FETs No Yes Yes Low
Ignore Fault
TON Max Fault TON_MAX_FAULT_LIMIT Latch-off Both FETs off No Yes Yes Low
Restart Both FETs off, then restart after 7×TON_RISE
Ignore PWM maintains control of FETs
VIN UVLO VIN_ON, VIN_OFF Shut down Both FETs off Yes Yes Yes Low
(1) When the overtemperature fault is tripped, the device shuts off both FETs and restarts until the sensed temperature decreases 20°C from the tripping threshold.
(2) The bandgap overtemperature Fault cannot be ignored, the device shuts off both FETs and restarts after the internal die temperature drops below the threshold.

NOTE

The best practice is to have the fault response of the loop master and slave device set as the same to avoid unexpected behavior.