SLUSCC7C July 2016 – June 2018 TPS546C23
Without the requirement of an external clock, the SYNC pin of the PWM-loop master device can be configured as SYNC-OUT and output a 50% duty-cycle clock to the slave device. The slave device is then synchronized to the falling edge of the clock applied to the SYNC pin. Both the loop master and slave devices require an RT resistor to set the free-running frequency. Figure 27 shows the simplified schematic for this configuration. For the loop slave device in a 2-phase configuration, the SYNC pin is always configured as SYNC-IN, and is synchronized to the falling edge of the incoming clock on the SYNC pin. Figure 28 shows the timing for phase interleaving.
An external clock can optionally be applied to both the PWM-loop master and the slave device to synchronize the stack. Only 50% duty cycle of the external clock can be applied to the 2-phase stack to realize the interleaving of two phases. The loop master automatically (auto) detects if an external clock is available for synchronisation. One clock master can also sync another stack as shown in Figure 29. When the auto detection determines the clock master and clock slave, the configuration cannot change until AVIN power cycling.
The EEPROM setup (FORCE_SYNC_IN Bit and FORCE_SYNC_OUT Bit) overrides auto detection of the SYNC pin. Therefore, if the FORCE_SYNC_OUT Bit is set to 1, the user should not apply the external clock to SYNC pin, which may cause catastrophic damage to the device. The FORCE_SYNC_IN Bit has higher priority than the FORCE_SYNC_OUT Bit. Neither the FORCE_SYNC_IN Bit nor the FORCE_SYNC_OUT Bit are set as a factory-default setting.