SLUSCC7C July 2016 – June 2018 TPS546C23
The devices prevent current from being discharged from the output during start-up, when a prebiased output condition exists. If the output is prebiased, no SW pulses occur until the internal soft-start voltage rises above the error-amplifier input voltage (FB pin). As soon as the soft-start voltage exceeds the error-amplifier input, and SW pulses start and the device limits synchronous rectification after each SW pulse with a narrow on-time. The on-time of the low-side MOSFET slowly increases on a cycle-by-cycle basis until 128 pulses have been generated and the synchronous rectifier runs fully complementary to the high-side MOSFET. This approach prevents the sinking of current from a prebiased output, and ensures the output-voltage start-up and ramp-to-regulation sequences are smooth and monotonic.
For prebias that is higher than regulation, the PWM-loop master device is forced to go through the 128 cycles of prebias operation at the end of TON_RISE time.
The output overvoltage warn is tripped when the FB pin is prebiased to higher than 5% about the regulation level. These devices respond to a prebiased output overvoltage condition immediately upon AVIN powered up and when the BP6 regulator voltage is above the BP6 UVLO of 3.73 V (typical).