SLVSHN0A September   2024  – October 2025 TPS548B23

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  D-CAP4 Control
      2. 6.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 6.3.2.1 Powering the Device From a Single Bus
        2. 6.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 6.3.3  Multifunction Configuration (CFG1-5) Pins
        1. 6.3.3.1 Multifunction Configuration (CFG1-2) Pins (Internal Feedback)
        2. 6.3.3.2 Multifunction Configuration (CFG1-2) Pins (External Feedback)
        3. 6.3.3.3 Multifunction Configuration (CFG3-5) Pins
      4. 6.3.4  Enable
      5. 6.3.5  Soft Start
      6. 6.3.6  Power Good
      7. 6.3.7  Overvoltage and Undervoltage Protection
      8. 6.3.8  Output Voltage Setting (External Feedback Configuration)
      9. 6.3.9  Remote Sense
      10. 6.3.10 Low-side MOSFET Zero-Crossing
      11. 6.3.11 Current Sense and Positive Overcurrent Protection
      12. 6.3.12 Low-side MOSFET Negative Current Limit
      13. 6.3.13 Output Voltage Discharge
      14. 6.3.14 UVLO Protection
      15. 6.3.15 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 6.4.2 Forced Continuous-Conduction Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Output Voltage Setting Point
        2. 7.2.2.2 Choose the Switching Frequency
        3. 7.2.2.3 Choose the Inductor
        4. 7.2.2.4 Choose the Output Capacitor
        5. 7.2.2.5 Choose the Input Capacitors (CIN)
        6. 7.2.2.6 VCC Bypass Capacitor
        7. 7.2.2.7 BOOT Capacitor
        8. 7.2.2.8 PG Pullup Resistor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.6 Power Good

The device has a power-good (PG or PGOOD) output that goes high to indicate when the converter output is in regulation. The power-good output is an open-drain output and must be pulled up to the VCC pin or an external voltage source (< 5.5V) through a pullup resistor (typically 30.1kΩ) to go high. The recommended power-good pullup resistor value is 1kΩ to 100kΩ.

Note: For systems using an external voltage source to pull up the PG pin, TI recommends that this same external voltage source also be used to bias the VCC pin.

After the soft-start ramp finishes, the power-good signal becomes high after a internal delay tPG_DLY. An internal soft-start done signal goes high when the SS voltage reaches VSS(DONE) to indicate the soft-start ramp has finished. If the FB voltage drops to 80% of the VREF voltage or exceeds 116% of the VREF voltage, the power-good signal latches low after a 3µs internal delay. The power-good signal can only be pulled high again after re-toggling EN or a reset of VIN.

If an OV event causes the FB voltage to exceed the OV threshold during soft start, but the FB voltage drops below the OV threshold before soft-start is completed, the power-good signal does not latch low until FB exceeds the OV threshold or drops below UV threshold. The OV or UV event must occur after the soft-start ramp finishes for the power-good signal to latch low. FB exceeding the OV threshold during soft start does, however, trigger the OV fault, and the devices response to OV (described in Section 6.3.7) typically pulls the output voltage below the UV threshold.

If the input supply fails to power up the device (for example, VIN and VCC both stay at zero volts) and this pin is pulled up through an external resistor, the power-good pin clamps low to the low-level specified in the POWER GOOD section in the Electrical Characteristics

TPS548B23 EN, SS, & PG Timing Diagram
Figure 6-3 EN, SS, & PG Timing Diagram