SLVSES4C September   2019  – June 2021 TPS54J060

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Enable and Internal LDO
      2. 7.3.2  Split Rail and External LDO
      3. 7.3.3  Output Voltage Setting
      4. 7.3.4  Soft Start and Output-Voltage Tracking
      5. 7.3.5  Frequency and Operation Mode Selection
      6. 7.3.6  D-CAP3 Control
      7. 7.3.7  Current Sense and Positive Overcurrent Protection
      8. 7.3.8  Low-side FET Negative Current Limit
      9. 7.3.9  Power Good
      10. 7.3.10 Overvoltage and Undervoltage Protection
      11. 7.3.11 Out-Of-Bounds Operation (OOB)
      12. 7.3.12 Output Voltage Discharge
      13. 7.3.13 UVLO Protection
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip Eco-Mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
      3. 7.4.3 Pre-Bias Start-up
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Choose the Switching Frequency and Operation Mode (MODE Pin)
        2. 8.2.2.2  Choose the Output Inductor (L)
        3. 8.2.2.3  Set the Current Limit (TRIP)
        4. 8.2.2.4  Choose the Output Capacitors (COUT)
        5. 8.2.2.5  Choose the Input Capacitors (CIN)
        6. 8.2.2.6  Feedback Network (FB Pin)
        7. 8.2.2.7  Soft Start Capacitor (SS/REFIN Pin)
        8. 8.2.2.8  EN Pin Resistor Divider
        9. 8.2.2.9  VCC Bypass Capacitor
        10. 8.2.2.10 BOOT Capacitor
        11. 8.2.2.11 Series BOOT Resistor and RC Snubber
        12. 8.2.2.12 PGOOD Pullup Resistor
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Support Resources
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Trademarks
    5. 11.5 Glossary
    6. 11.6 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Ordering Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.2.11 Series BOOT Resistor and RC Snubber

A series BOOT resistor can help reduce the overshoot at the SW pin. As a best practice, include a 0-Ω series BOOT resistor in the design for 12-V or higher input applications. The BOOT resistor can be used to reduce the voltage overshoot on the SW pin to within the Absolute Maximum Ratings in case the overshoot is higher than normal due to parasitic inductance in PCB layout. Including a 0-Ω BOOT resistor is recommended with external VCC as the SW node overshoot is increased. The recommended BOOT resistor value to decrease the SW pin overshoot is 4.7 Ω.

An RC snubber on the SW pin can also help reduce the high frequency voltage spikes and ringing at the SW pin. Recommended snubber values are 6.8 Ω and 220 pF. The best value for these components can vary with different layouts but these recommended values should provide a good starting point. In order for the RC snubber to be as effective as possible, it should be placed on the same side as the IC and be as close as possible to the SW pins with a very low impedance return to PGND pins.