SLVSFQ8A December   2020  – December 2021 TPS552882-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  Operation Mode Setting
      3. 7.3.3  Input Undervoltage Lockout
      4. 7.3.4  Enable and Programmable UVLO
      5. 7.3.5  Soft Start
      6. 7.3.6  Shutdown
      7. 7.3.7  Switching Frequency
      8. 7.3.8  Switching Frequency Dithering
      9. 7.3.9  Inductor Current Limit
      10. 7.3.10 Internal Charge Path
      11. 7.3.11 Output Voltage Setting
      12. 7.3.12 Output Current Indication and Cable Voltage Drop Compensation
      13. 7.3.13 Integrated Gate Drivers
      14. 7.3.14 Output Current Limit
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Output Short Circuit Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Power Save Mode
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Switching Frequency
        3. 8.2.2.3 Output Voltage Setting
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Input Capacitor
        6. 8.2.2.6 Output Capacitor
        7. 8.2.2.7 Output Current Limit Sense Resistor
        8. 8.2.2.8 Loop Stability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Glossary
    6. 11.6 Electrostatic Discharge Caution
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents, layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and noise problems. To maximize efficiency, switching rise time and fall time are very fast. To prevent radiation of high-frequency noise (for example, EMI), proper layout of the high-frequency switching path is essential. Minimize the length and area of all traces connected to the SW1 and SW2 pins, and always use a ground plane under the switching regulator to minimize interplane coupling. The input capacitor needs to be close to the VIN pin and the PGND to reduce the input supply current ripple.

The most critical current path for buck converter portion is from the switching FET at the buck side, through the rectifier FET at the buck side to the PGND, then the input capacitors, and back to the input of the switching FET. This high current path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the input capacitor for power stage must be close to the input of the switching FET and the PGND terminal of the rectifier FET.

The most critical current path for boost converter portion is from the switching FET at the boost side, through the rectifier FET at boost side, then the output capacitors, and back to ground of the switching FET. This high current path contains nanosecond rise time and fall time, and should be kept as short as possible. Therefore, the output capacitor needs not only to be close to the VOUT pin, but also to the PGND pin to reduce the overshoot at the SW2 pin and the VOUT pin.

The traces from the output current sensing resistor to the ISP pin and the ISN pin must be in parallel and close to each other to avoid noise coupling.

The PGND plane and the AGND plane are connected at the terminal of the capacitor at the VCC pin. Thus the noise caused by the MOSFET driver and parasitic inductance does not interfere with the AGND and internal control circuit.

To get good thermal performance, it is recommended to use thermal vias beneath the TPS552882-Q1 connecting the PGND pin to the PGND plane, and the VOUT pin to a large VOUT area separately.