SLVSGA9A March   2022  – August 2022 TPS55289

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VCC Power Supply
      2. 7.3.2  EXTVCC Power Supply
      3. 7.3.3  Operation Mode Setting
      4. 7.3.4  Input Undervoltage Lockout
      5. 7.3.5  Enable and Programmable UVLO
      6. 7.3.6  Soft Start
      7. 7.3.7  Shutdown and Load Discharge
      8. 7.3.8  Switching Frequency
      9. 7.3.9  Switching Frequency Dithering
      10. 7.3.10 Inductor Current Limit
      11. 7.3.11 Internal Charge Path
      12. 7.3.12 Output Voltage Setting
      13. 7.3.13 Output Current Monitoring and Cable Voltage Droop Compensation
      14. 7.3.14 Output Current Limit
      15. 7.3.15 Overvoltage Protection
      16. 7.3.16 Output Short Circuit Protection
      17. 7.3.17 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 PWM Mode
      2. 7.4.2 Power Save Mode
    5. 7.5 Programming
      1. 7.5.1 Data Validity
      2. 7.5.2 START and STOP Conditions
      3. 7.5.3 Byte Format
      4. 7.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)
      5. 7.5.5 Target Address and Data Direction Bit
      6. 7.5.6 Single Read and Write
      7. 7.5.7 Multiread and Multiwrite
    6. 7.6 Register Maps
      1. 7.6.1 REF Register (Address = 0h, 1h)
      2. 7.6.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100h]
      3. 7.6.3 VOUT_SR Register (Address = 3h) [reset = 00000001h]
      4. 7.6.4 VOUT_FS Register (Address = 4h) [reset = 00000011h]
      5. 7.6.5 CDC Register (Address = 5h) [reset = 11100000h]
      6. 7.6.6 MODE Register (Address = 6h) [reset = 00100000h]
      7. 7.6.7 STATUS Register (Address = 7h) [reset = 00000011h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching Frequency
        2. 8.2.2.2 Output Voltage Setting
        3. 8.2.2.3 Inductor Selection
        4. 8.2.2.4 Input Capacitor
        5. 8.2.2.5 Output Capacitor
        6. 8.2.2.6 Output Current Limit
        7. 8.2.2.7 Loop Stability
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.5 CDC Register (Address = 5h) [reset = 11100000h]

CDC is shown in Figure 7-20 and described in Table 7-9.

Return to Summary Table.

Register 05h sets masks for SC bit, OCP bit, and OVP bit in register 07h. In addition, register 05h sets the voltage rise added to the setting output voltage with respect to the sensed differential voltage between the ISP pin and the ISN pin.

Figure 7-20 CDC Register
76543210
SC_MASKOCP_MASKOVP_MASKRESERVEDCDC_OPTIONCDC
R/W-1bR/W-1bR/W-1bR/W-0bR/W-0bR/W-000b
Table 7-9 CDC Register Field Descriptions
BitFieldTypeResetDescription
7SC_MASKR/W1bShort circuit mask

0b = Disabled SC indication

1b = Enable SC indication (Default)

6OCP_MASKR/W1bOver current mask

0b = Disabled OCP indication

1b = Enable OCP indication (Default)

5OVP_MASKR/W1bOver voltage mask

0b = Disabled OVP indication

1b = Enable OVP indication (Default)

4RESERVEDR/W0bReserved
3CDC_OPTIONR/W0bSelect the cable voltage droop compensation approach.

0b = Internal CDC compensation by the register 05H (Default)

1b = External CDC compensation by a resistor at the CDC pin

2-0CDCR/W000bCompensation for voltage droop over the cable

000b = 0-V output voltage rise with 50 mV at VISP - VISN (Default)

001b = 0.1-V output voltage rise with 50 mV at VISP - VISN

010b = 0.2-V output voltage rise with 50 mV at VISP - VISN

011b = 0.3-V output voltage rise with 50 mV at VISP - VISN

100b = 0.4-V output voltage rise with 50 mV at VISP - VISN

101b = 0.5-V output voltage rise with 50 mV at VISP - VISN

110b = 0.6-V output voltage rise with 50 mV at VISP - VISN

111b = 0.7-V output voltage rise with 50 mV at VISP - VISN